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David Buchanan ,
Product Applications Engineer Manager, Analog Devices

My ADC specifies 12-bit linearity, but 10.5 ENOB. Do your specifications break the rules?

RAQs Issue 90Recently an old friend and colleague retired. While cleaning out his office he reminded me that he was the “Official Keeper of the Ancient Data Sheets.” That’s right; the rare hard copies of product data sheets that were published—and obsolete—long before today’s ubiquitous digital documentation. My friend was not unlike the Beadle of the Presbyterian Church in old Scotland, whose duties included taking care of the church’s Bible in the days when there might have been only one in any given church. He informed me that he had chosen me as his successor. No smoke signals from a room full of old men or anything like that, but I may have been lucky enough to have the closest office with someone he could trust to assume this awesome responsibility.

As my friend and I reminisced about a few of the old winners and losers, I remembered having just answered a customer’s question about an ADC’s effective number of bits (ENOB). ENOB is based on the equation for an ideal ADC’s SNR: SNR = 6.02 × N + 1.76 dB, where N is the ADC’s resolution. A real world ADC never achieves this SNR due to its own noise and errors. You can rearrange the equation to calculate an ADC’s effective N, or ENOB as we commonly call it: ENOB = (SNR – 1.76)/6.02 dB. The part that we were discussing was a 12-bit ADC, but the ENOB was only 10.5. The customer was very polite, but felt compelled to point out that it seemed inappropriate to describe an ADC as having 12-bit resolution when it was missing 1.5 bits of performance. The part in question operated at 500 MSPS, which was very fast for the power it required. The customer pressed me as to whether we might have exaggerated the resolution. He acted like we were breaking the rules! I explained that the rule we don’t break is linearity; the converter’s differential linearity must be <1 LSB at the specified resolution. Also, the converter’s integral linearity determines its distortion performance, so converters with higher resolution can achieve higher SFDR.

As I told my friend the story, he knew where I was headed. We had just talked about a 12-bit ADC that was a real winner 25 years ago, when the state of the art throughput rate was 50 times slower—only 10 MSPS. We pulled out the old data sheet, and sure enough, it was 10.5 ENOB!


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  • About The Author
  • David Buchanan
    Product Applications Engineer Manager, Analog Devices

David Buchanan received a BSEE from the University of Virginia in 1987. Employed in marketing and applications engineering roles by Analog Devices, Adaptec, and STMicroelectronics, he has experience with a variety of high-performance analog semiconductor products. He is currently a senior applications engineer with ADI’s High Speed Converters product line in Greensboro, North Carolina.