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Ian Beavers ,
High Speed ADC Applications Engineer, Analog Devices

When using an ADC's internal digital downconversion (DDC) processing for decimation, my single tone real input signal is losing 6 dB of power. What is happening?

Many high speed ADCs now provide digital postprocessing functions, after the core analog-to-digital conversion, to allow additional flexibility in signal acquisition systems. One common signal processing block is digital downconversion. A DDC is used to narrow an ADC's bandwidth, reduce the amount of output data sent to the downstream signal chain, and achieve additional processing gain for the smaller signal bandwidth of interest. Its primary function is to act as a complex mixer by converting a digitized real signal, centered relative to a known frequency, to a baseband complex signal centered at zero frequency. DDCs are also commonly used with a complex input signal.

The DDC function within an ADC provides three components to process real sampled data:

  • A numerically controlled oscillator (NCO) to generate a complex quadrature sinusoid frequency to a digital mixer.
  • A low-pass digital filter to narrow the sampled bandwidth—commonly implemented with a finite impulse response filter (FIR).
  • A downsampler for decimation of the ADC data.

RAQ - Issue 124, Figure 1


Figure 1. Digital downconversion is composed of a complex NCO mixed with real data, which is then filtered and decimated to create both an I&Q output data stream.

The first stage of the DDC is a function to mix, or multiply, the ADC output with a cosine for the phase data and a sine for the quadrature data, generating sum and difference frequency components. Multiplication of the complex NCO frequency with the input signal creates images that are centered at the sum and difference frequency. The low-pass filter will pass the difference frequency, within the chosen frequency bandwidth, while rejecting the sum frequency image. The DDC output results in a complex representation of the original signal with I&Q data.

If either the I&Q data output is processed and interpreted separately, signal power may appear to have been lost. But, since the I&Q data have been split, with an accompanied reduction in filtered noise spectral density, the signal power appears lower relative to the ADC full-scale range. This can result in what falsely seems to be a signal with 6 dB less power or a half signal. However, the new complex signal is mathematically equivalent to the real original, albeit filtered, but the power is now split between I&Q data.


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  • About The Author
  • Ian Beavers
    High Speed ADC Applications Engineer, Analog Devices

Ian Beavers is a product engineering manager for the Automation Energy & Sensors team at Analog Devices (Greensboro, NC). He has worked for the company since 1999. Ian has over 19 years of experience in the semiconductor industry. Ian earned a bachelor's degree in electrical engineering from North Carolina State University and an M.B.A. from the University of North Carolina at Greensboro.