ADV202 - FAQ
What does the J2KPROG encode parameter mean?
Every tile contains packets that make up the coded tile. These packets contain information about a specific layer, component, resolution level and a specific position. The J2KPROG encode parameter allows the user to program the order in which packets are arranged in the codestream.
More detailed information on Progression Order can be found in the ISO/IEC15444-1 standard, Annex B.12.
What information does the ADV202/212 header contain?
The 16-byte header starts with a Field ID 4-byte value, followed by an image index number and information about the encoded format . The last 4 bytes contain the size of the compressed field/frame in Number of 32-bit words contained in the compressed field/frame. This value does not include the 16-byte header.
Detailed byte description about this header can be found at:
What are Multilayers?
Multilayer codestream means, that the JPEG2000 output stream contains several layers of which each layer contains data compressed at a different compression ratio. The number of layers can be programmed with the ADV202/212.
On the decoding side it is then possible to extract a particular layer only.
The data has to be encoded in Multilayer mode. To do this, the JPEG2000 parameter RCTYPE is set to Multi-layered Target Size or Multi-layered Target Quality. The number of layers is then set with the RCTYPE value. The amount of compression for each layer is set with the LTARGET parameter.
Refer to the Programming Guide for more information.
Multi-layered compression is implemented with the ADV202-PCI HD card. Refer to the Alberio User Guide for more information:
What does encode parameter VFORMAT De-interlace mean?
Using de-interlace mode improves compression efficiency by 40% to 50%. In de-interlace mode, two consecutive fields are compressed together. In non-de-interlaced mode, each field is compressed individually.
De-interlaced mode is useful for network applications or low bandwidth applications where encode and decode are performed by the ADV2x2.
VFORMAT de-interlace can be used for NTSC or PAL.
In decode, de-interlace mode is only a valid decode mode if the compressed input codestream is a previously encoded ADV2x2 codestream that has been encoded with VFORMAT set to de-interlaced.
What are 9/7 and 5/3? How do I know which one to use?
9/7 and 5/3 refers to the number of wavelet filter coefficients used in the wavelet transform filters. A 5/3 filter has five taps for the low-pass filter and three taps for the high-pass filter. 9/7 and 5/3 filters have different memory requirements, so input image width requirements change as documented in Table 25 in the datasheet for your product.
What is the highest transfer rate for data and control?
DMA transfers allow a maximum load on the HDATA interface of 200 MBytes/sec if 32-bit host is used and both DMA channels are active.
As per datasheet the maximum compressed data output rate is 200Mbits/sec.
What is the difference between direct and indirect registers?
Direct registers must always be configured regardless of the application. They set the data and control width, operating frequency and all other necessary configurations to access the ADV202/212.
Indirect register configuration is required to set specific data transfer modes or configure the ADV202/212 for specific input formats.
Refer to the ADV202/212 Programming Guide for information when indirect registers must be used.
Direct registers are accesses with a standard RD/ or WR/, CS/, ACK/, ADDR[3:0] and HDATA [15:0] or HDATA[31:0] protocol.
Indirect registers are accessed over direct registers using Normal Host Mode. The direct registers IADDR and IDATA are used to access indirect registers. Refer to the ADV202/212 Programming Guide and datasheet for more detail.
What is the HDATA impedance state?
If RESET/ is low or CS/ and RD/ and WE/ are high, then HDATA is high impedance.
What is Fly-By DMA used for?
In fly-by mode DMA, the function of the RD and WE signals (for DMA only) are reversed. This allows a host to move data between an external device and the ADV202/212 with the use of a single strobe.
In encode mode with fly-by DMA, the host can use the RDFB signal (WE pin) to simultaneously read from the ADV202/212 and write to an external device like memory.
In decode mode with fly-by DMA, the host can use the WEFB signal (RD pin) to simultaneously read from the external device and write to the ADV202/212.
What are the recommended configuration and parameter settings for PAL?
Recommended parameter settings for PAL 8-bit video with 288 x 720 @ 50Hz active field rate, YCbCr [4:2:2] with embedded timecodes as input on VDATA [11:4]:
What are the advantages of JDATA streaming mode?
The advantage of using JDATA streaming mode is that registers can be written to and read from while JDATA data transfer is taking place. On the other hand, JDATA mode allows only a 8-bit wide compressed data output stream and can only be used for 16-bit host interface applications. See the ADV212 Programming Guide for JDATA mode configuration examples.
What is the host interface used for?
The host interface is used for configuration of the ADV202/212 and for transfering compressed data to/from the ADV202/212.
In Host Interface/Pixel Interface [HIPI] mode, it is also used for uncompressed pixel input/output.
Refer to AN-790 for more information on the function of the host interface.
What is the difference between the DREQ/DACK and DCS DMA modes?
Both DREQ/DACK mode and dedicated chip select (DCS) are DMA modes. DCS mode allows more control of the data through the FFTHRC register, since DREQ/DACK modes are fixed to single or the programmed burst sizes.
In DREQ/DACK DMA mode, the DREQ/ asserts as soon as sufficient data is present to fullfill the DMA burst or DMA single access settings in the EDMOD registers. DREQ/ assert should be answered with an DACK/ assert from the host processor.
DREQ/DACK mode and DCS mode require the DREQ/ and DACK/ pins. However, the functionality of these pins is slightly different in the two modes.
See the ADV212 Programming Guide for more information on DREQ/DACK and DCS DMA modes. See the ADV212 User's Guide for more information on the threshold registers.
What evaluation systems are available for the ADV202/212?
1. ADV202/212 ASD P160 EB is an ADV202/ADV212 daugther card designed for a Memec Xilinx Spartan 3SXLC motherboard.
Input: analog NTSC or PAL in CVBS or S-Video format
Output: analog NTSC or PAL in CVBS or S-Video format The boards can be used in a stand-alone application. In this case modes are controlled over DIP switches.
In PC control mode access to registers, parameter settings is possible. The board is controlled over a USB connection to a PC using the Hyperterminal interface.
In Developer Mode, access to source code is available.
Interface is Xilinx EDK and ISE over a JTAG connector.
2. The ADV202/212-HD-EB is a 32-bit PCI card.
Input : 1080i or 720p SDI video
Output: 1080i or 720p SDI video One card can be used for either encode or decode. Two cards can be used in the same PC for a encode-decode pass-thru demonstration.
The card is mainly intended for evaluation JPEG2000 compression of High Definition video.
What is the difference between the ADV202 and the ADV212?
The ADV202 and ADV212 are functionally the same, except that the ADV212 has an additional JTAG interface for boundary scan description language (BSDL). The ADV212 requires up to 50% less power than the ADV202.
The ADV202 and the ADV212 have the same footprint and pin-out.
Release notes for each product are available at:ADV202 PCN and Errata
ADV212 PCN and Errata
If leaded ADV202 parts are replaced by lead-free ADV212 parts, the soldering requirements will change. See the datasheet of the relevant product for soldering requirements:ADV202 JPEG2000 Video Codec
ADV212 JPEG2000 Video Codec
What is the compression rate of the ADV202/ADV212?
The compression rate is not defined in the JPEG2000 ISO/IEC15444-1 standard which is implemented on the ADV202/212.
Any compression rate can be programmed with the ADV202/212 encode parameters.
The part can be configured to provide a fixed compression rate with a variance of +5% of the programmed value, down to -100% of the programmed value.
The compression rate is programmed with the RCType and RCVal encode parameters [refer to Programming Guide].
What does 'positive' / 'negative' polarity mean for HVF and VCLK?
Positive polarity means that the active edge is a low-to-high transition. Negative polarity means that the active edge is a high-to-low transition.
Both the firmware encode parameter PICFG and the PMODE2 register allow you to change the polarity of HSYNC, VSYNC, FIELD, and VCLK.
Polarity is set with the PMODE2 register if the register is programmed for custom-specific mode or raw pixel mode. Otherwise, polarity is set with the ADV2x2 firmware encode parameter PICFG.
What does the PULS field in the EDMOD registers do?
The ADV202/212 allows the DREQ/ pulse to be configured in two ways:
- DREQ/ is asserted until the host processor responds with a DACK/ assert. This requires the DRxPULS bits in the EDMODx register to be set to '0000'.
- DREQ/ pulse width is programmable and does not require a DACK/ for DREQ/ de-assertion. The pulse width is set with the DRxPULS bits in the EDMODx registers.
Refer to the datasheet for timing diagrams for both modes.
What are precincts and does the ADV202/212 support precincts?
Precincts are not supported with the presently available firmware for the ADV202/212.
Precincts are further partitions of a tile which allow access to individual codeblocks. Precincts allow extraction of particular areas within a tile.
For more information on precincts refer to David S. Taubman and Michael W. Marcellin's JPEG2000: Standard for Interactive Imaging article.
What is the ADV202/ADV212?
The ADV2x2 is designed to provide a hardware solution for JPEG2000 compression. The ADV2x2 doesn't provide JPEG or MPEG compression.
The ADV2x2 allows seamless input of most common video formats such as NTSC, PAL, 1080i, or 720p.
The ADV2x2 provides JPEG2000 output compliant to the ISO/IEC1544-1 standard in JP2 and J2C formats.
An overview of ADV2x2 operation and operational requirements can be found in the AN-790 application note.
What are the recommended configuration and parameter settings for NTSC?
Recommended parameter settings for NTSC 8-bit video with 242 x 720 @ 60Hz active field rate, YCbCr [4:2:2] with embedded timecodes as input on VDATA [11:4]:
In NTSC master decode the ADV202/212 is configured to generate a blanking region of 14 lines starting on line # 10 and line # 273 after the Field bit transition.
What happens if the HVF inputs do not match dimension register settings?
The output will very likely show skipped fields or skipped lines.
What is a .sea file?
This is the file extension for the ADV2x2 firmware. The file extension stands for software embedded application and is not an official file extension format. The firmware is in binary format.
The vertical blanking between fields/frames varies on my input source. What mode should I use?
It is recommended to use Raw Pixel Video mode. Refer to the ADV202/212 Programming Guide for Raw Pixel Video configuration.
Must DMA always be used for compressed data input/output?
No. Other modes for compressed data input/output are JDATA mode or Normal Host Mode using thresholds.
Refer to AN-790 for a general description of these modes and the ADV202/212 Programming Guide for configuration examples of these modes.
Is it possible to encode and decode different frame sizes without reloading the firmware?
On-the-fly changes of field/frame sizes is not supported.
Changes in field/frame size require a re-configuration of the dimension registers and a reboot procedure.
Is the ADV202/212 output compatible with any JPEG2000 software codecs?
Yes. The ADV202/212 compressed output, if .j2c or jp2 format, is fully compatible to the ISO/IEC 15444-1 JPEG2000 standard.
Note, the ADV202/212 will insert a 16-byte header at the start of each codestream. This header has to be removed in order for other JPEG2000 codecs to recognize the codestream correctly.
Commonly used with the ADV202/212, Kakadu is a free of charge software codec from www.kakadusoftware.com
Is the VDATA bus the only interface to input/output video/pixel data?
VDATA does not have to be used to input pixel data.
It is possible to use the HDATA bus alone for uncompressed pixel data/ compressed data transfers. This is faciliated in using the 2 DMA channels provided by the ADV202/212.
Using the HDATA interface alone for transfer of compressed/uncompressed data is called Host Interface Pixel Interface [HIPI] mode.
How to use encode parameters RCtype and RCval
Refer to the RCTYPE and RCVAL section, page 53-56 of the Programming Guide for instructions on how to calculate compression rate.
How to determine latency?
The ADV202's latency is generally 1.5 fields in encode or decode mode.
If frames are input, the the latency is in frames.
ADI does not provide exact specification of latency, since it depends on a lot of factors which would make an exact specification difficult.
Complexity of input image, # of wavelet transform levels, choice of wavelet filters, choice of output format will all effect latency but nevertheless it will be kept in the 1.5 fields/frames range.
In order for the ADV202 to perform the rate control calculations, i.e. determine the compression ratio to keep a certain bit rate, or determine the compression ratio to keep a certain quality, it requires the wavelet information of one field/frame to be present on internal memory. Once the information of an entire field/frame is present the rate control calculation can be performed and the data can be output. Latency can be reduced in using single component input, 5/3 irreversible compression mode, .j2c output format, codeblock size of 128x32.
How to extract low resolution packets from one JPEG2000 stream
The JPEG2000 stream contains information about different resolutions of the original input. The scalability feature of JPEG2000 allows to extract a lower resolution only, if this is required by the application.
In order to extract a low resolution version of the original data, set progression order to LRCP and enable PLT [Packet length, Tile Part header] markers.
Refer to the Programming Guide, Encode Parameter section.
The JPEG2000 stream is then output in the following order:
Y, Resolution 0 [smallest, contains only resolution 0]
Cb, Resolution 0 [smallest, contains only resolution 0]
Cr, Resolution 0 [smallest, contains only resolution 0]
Y, Resolution 1 [ contains resolutions 0 and 1]
Cb, Resolution 1 [contains resolutions 0 and 1]
Cr, Resolution 1 [contains resolutions 0 and 1]
Y, Resolution 5 [contains resolutions 0, 1, 2, 3, 4, 5]
Cb, Resolution 5 [contains resolutions 0,1,2,3,4,5]
Cr, Resolution 5 [contains resolutions 0,1,2,3,4,5]
Then extract for each component the required resolution packets. The PLT marker starts with code 0xFF58 and its header will include the length of this packet.
The main header would then have to be changed to:
- In the SIZ marker, change the Xsiz, Ysiz, XTsiz, and YTsiz values to reflect the new image dimensions.
- In the COD marker (SPcod parameter), change the number of decomposition levels accordingly, for example if resolution 4 is extracted, use 4 instead of 5.
How do I determine the number of codeblocks per image?
Codeblocks are a result of the JPEG2000 compression process. Codeblocks are generated from the wavelet coefficient data after the pixel data has passed the wavelet filters. The number of codeblocks generated depends on the input resolution, codeblock size, number of transform levels, and the number of components.
Codeblock size can be changed with the CBSIZE firmware encode parameter.
Generally, standard definition (SD) resolutions do not require any particular codeblock size setting. For high definition (HD) resolutions, set the codeblock size to the maximum in order to keep the number of codeblocks generated below the maximum limit. (At present, the maximum number of codeblocks that the ADV2x2 can process is 610 per image, field, or frame.)
The technical note "How to estimate the number of codeblocks/image" explains how to estimate the number of codeblocks generated for a particular input resolution and CBSIZE setting.
How to change the video input rate to the ADV202/212
The encode parameter STALLPAR can be used to decrease the input field rate to be encoded, so that only every 2nd, 3rd or 4th etc field is encoded.
The STALLPAR can be programmed prior to starting the encoding process or can be changed during the encode process.
It is also possible to use the STALLPAR to halt encoding momentarily in setting STALLPAR to its maximum value of 0xFF and back to 0x00 to start encoding again.
How to change the compression ratio from field to field without reloading the firmware
In order to change the compression ratio on the fly, SWIRQ2 in the EIRQIE register must be enabled.
When the interrupt flag for SWIRQ2 in EIRQFLG is then set, it means that the RCVAL will be applied to the compressed field right after this interrupt. This does not apply to RCTYPE. RCTYPE can not be changed on a field by field basis with the present firmware.
RCVAL changes on the fly are supported with firmware version encode_2_7_p.sea upwards.
How should the CFG pins be connected?
On the ADV202/212 the hardware boot from the CFG pins is not implemented. Boot mode is only recognized by the register setting in the BOOT MODE register.
In encode mode, is it required to read out the previous field before the next field is input?
No, it is not required to entirely read out a compressed field before the next can be input.
How to use the ADV202/212 with multiple-camera input
If video sources are switched while the ADV202/212 is processing a field/frame the present field/frame will be flushed out of memory and the ADV202/ADV212 will wait for the next available valid synchronisation signal.
This will be the next in-active Vsync edge if HVF are used, or the next valid EAV/SAV code.
The ADV202/212 will not be able to identify which source has been used although it will update the image index value in the ADV2x2 header for every consecutive field/frame received. The ADV2x2 header is a 16-byte header that is inserted at the start of every field/frame/image before the JPEG2000 headers.
How to input video that is not ITU.R.BT656
For any video input that is not CCIR656 PAL or NTSC, SMPTE274M [1080i] or SMPTE296 [720p] Custom Specific mode must be used.
Custom Specific mode allows video input in any interlaced or progressive format as long as data input rate limits are met.
Refer to the ADV202/212 Programming Guide for configuration for Custom Specific mode.
How to input RGB data to the ADV202/212
The ADV202/212 does not support direct input of RGB data on the VDATA or HDATA bus.
It does support input in single component format, so that either R or G or B can be input on the VDATA or HDATA bus.
For RGB applications it is therefore recommended to use the ADV202/212 in single component mode or to convert RGB to YCbCr 4:2:2 prior to encoding.
I have "video on demand". Can I put the ADV202/212 in a pause state in encode mode until video or an image is available again?
Yes. If video with HVF syncs are used and input video is lost, the ADV202/212 will wait for the next available in-active Vsync transition. Re-configuration and re-loading of firmware is not necessary as long as the format has not changed. If video with EAV/SAVs are used, the ADV202/212 will wait for the next valid EAV/SAV codes and continue encoding again.
It is also possible to use the encode STALLPAR and set it to its maximum value of 0xFF to disable encoding and set it back to 0x00 to start encoding again.
How should I connect unused VDATA pins and HDATA pins?
Unused VDATA and HDATA pins should be tied to ground via a pull-down resistor.
How to program compression rate
Refer to the RCTYPE and RCVAL section, page 53-56 of the Programming Guide for instructions on how to calculate compression rate.
How many ADV202/212s can I connect together on the HDATA bus in a multi-chip application?
It is recommended to use 4 or less ADV202/212s sharing the same HDATA bus.
In DMA burst mode, what if the last burst does not contain the number of bursts specified as in the EDMOD register?
If the last burst in the FIFO does not contain the number of bursts specified in the EDMOD register, the ADV202/212 will insert 0es to the programmed burst boundary to faciliate access to the last data bytes in the FIFO.
How is the optimal DMA burst length determined?
Generally a setting of 16 bursts will be an adequate setting for both 16-bit and 32-bit interfaces. 16-bit interfaces should use burst length of 16 or higher. Burst size could then be increased or decreased to best fit application requirements. It is important that burst requests [DREQ/ assert] are to be serviced immediately in order to avoid FIFO over- or underflows.
Burst length of 512 for 32-bit interfaces and burst length of 1024 for 16-bit interfaces are not recommended.
How do I determine the number of ADV2x2s required for a particular application?
There are two main factors that help you estimate how many ADV2x2s to use:
- Image size: the actual number of pixels in each frame. Each ADV2x2 has a maximum image size of 1.048 Msamples. Images larger than this must be tiled prior to being input to the ADV2x2.
- Throughput: the number of pixels per second. Each ADV2x2 has a maximum throughput of 65 Msamples per second (active resolution).
You need to determine which of these requirements is the largest for your application and to use the number of ADV2x2s that meets that larger requirement. In addition to these two major factors, there are other factors that influence how many ADV2x2s you may need. You may have to experiment with tradeoffs to get the right number of chips with the quality you want.
Image size is limited to 1.048 Msamples per image to support all of the JPEG2000 features that the ADV2x2 provides. This applies to all compression modes (9/7i, 5/3i, 5/3r).
The samples per image = horizontal active resolution x vertical active resolution x number of components per pixel.
NTSC 720 x 242 YCbCr 4:2:2 format (NTSC requires fields, not images or frames)
samples/field = 720 x 242 x 2 = 348,480 samples/field
348,480 samples/field is less than the limit of 1.048 Msamples, so if the maximum throughput is not exceeded, only one ADV2x2 is required.
The root of the image-size limitation is the way the compression rate is controlled. Before the rate control algorithm is applied, the wavelet coefficients for an entire image must be present in memory. From this information, the best fit quality or size value is applied to the image.
The fact that all the memory is allocated dynamically complicates the situation. This means that there is no specified amount of memory that is available at any one time. The amount of memory depends on the content of the image currently being compressed as well as the content of the next image. For this reason, the ADV2x2 has a relatively conservative image-size limitation of 1.048 Msamples. This is roughly equal to the amount of data in a 1080i luminance or chrominance field.
The second main limitation, throughput, is determined by the clock speed of the part itself. Input data rate limits are listed in the datasheet. Maximum input data rate is achieved on the VDATA bus. For the ADV2x2 with a speed grade of 150 MHz, the maximum throughput on the VDATA bus is 65 Msamples/sec (active resolution) or 74.25 Msamples/sec (total resolution). On the HDATA bus, the maximum throughput is 45 Msamples/sec.
If the image size isn't exceeded, you can always try to reduce the number of chips based on this limitation by slowing down the number of frames per second.
NTSC 720 x 242 at 60 Hz YCbCr 4:2:2 format
input data rate = 720 x 242 x 2 x 60 = 20.9 Msamples/sec
20.9 Msamples/sec is less than the limit of 65 Msamples/sec, so if the maximum image size is not exceeded, only one ADV2x2 is required.
720p / 60 FPS YCbCr 4:2:2
1280 x 720 x 2 samples per x 60 FPS = 110.6 Msamples/second
[110.6 / 65] Msamples/sec per ADV212 = 1.7 = 2 ADV212s
1280 x 720 x 2 samples per pixel = 1,843,200 samples per tile
1,843,200 sample per tile / 1,048,000 samples per ADV212 = 1.75 = 2 ADV212s.
This application would require 2 ADV212s.
I require a compression system with extreme low latency
The ADV202/212 has a latency of approx. 1.5 fields/frame/image in encode and approx. the same latency in decode mode.
This means, if a field, frame or image has an input rate of 10ms/field,frame or image then the latency will be approx. 15 ms in encode mode.
How to display ADV202/212 compressed files on PC screen
The ADV202 Alberio software allows previously ADV202/212 compressed video or still images to be displayed on a PC screen without the requirement of having a ADV202/212 PCI evaluation card installed in the decoding system.
This is explained in the Alberio User Guide at:
How to configure the ADV202/212 for 4Kx4K input images
If the image data is monochrome, It is required to tile the input into 16 1K x 1K tiles before compression and send them sequentially to the ADV202/212. Considering the HDATA data input rate limitations, this would allow an input rate of approx. 40 images/sec.
For color images the images would have to be tiled further to stay under the maximum image size limit of 1.048 Msamples/image.
A recommended configuration for this application is to use HIPI mode.
For a general overview of HIPI mode refer to: ADV202 HIPImode Still Image Application
This mode expects the image data to be in pixel raw format with no timing information associated with the pixel data. Pixel data can be monochrome or YCbCr 4:2:2 data. How the pixel data should be aligned on the 32-bit HDATA bus is covered in the ADV202/212 User's Guide.
Apart from the direct register configuration, the following indirect register must be configured for this particular configuration:
Timing specification for DREQ/DACK Burst Mode can be found in the ADV202/212 datasheet.
EDMOD registers should stay disabled while they are configured and should be enabled before clearing EIRQFLG 0x0400 to start the program. Refer to the ADV202/212 Programming Guide for recommended programming sequence.
Recommended Encode parameter settings:
Encode and decode parameters PREC, UNI, PICFG are ignored in HIPI mode. They must be set with the indirect register accesses mentioned above.
Recommended Decode parameter settings:
Once the program is started DMA channel 0 will assert DREQ0/ requesting uncompressed data to be input into the Pixel FIFO. As soon as compressed data is available DREQ1/ will assert. This generally happens after 1 complete image has been input.
For most robust data transfer, it is recommended to service the DREQ/s in a round-robin fashion once both are asserting. This means service burst from DREQ0/, then service burst from DREQ1/.
Images can be input continuously. It is not required to read out all the compressed image data for one image before the next image can be input. Individual images are identified in the ADV202/212 generated header with the image index number. The ADV202/212 header will be inserted at the start of each compressed image.
The ADV202/212 will not merge the sixteen tiles into a complete image. This must be done externally.
Is it possible to bypass the ADV202/ADV212 compression?
No. Regardless of what encode parameter settings are used and with the presently available firmware, all uncompressed data is passed through the Wavelet Filters and Entropy Codecs.
In encode mode, how do I know if the ADV202/212 is ready to output data?
Depending on what mode is used to output data the ADV202/212 will indicate when it is ready to output data:
In Normal Host Mode: CODE FIFO threshold flag is set. Refer to the ADV202/212 Programming Guide for configuration example.
In JDATA Mode: VALID is asserted. Refer to the ADV202/212 Programming Guide for a configuration example and the System Register section in the User's Guide.
In any DMA mode: DREQ/ is asserted. Refer to the ADV202/212 Programming Guide for a configuration example and the System Register section in the User's Guide.
How does the ADV202/212 handle VBI or CC data?
VBI data or CC data which is contained in the vertical blanking region is ignored by the ADV202/212 and will be lost during the compression process.
How does the ADV202 recover from data input loss in encode or decode mode?
In particular applications it can not be avoided that a loss of source input does occur.
If the ADV202 is in encode mode and the source is lost during a field, the present data will be flushed out of memory and the ADV202 will wait until the next valid field is input. Reloading the firmware is not necessary.
If data is input on the VDATA on the clock input on VCLK is lost, then encode will stop until a valid clock input is available again.
In decode mode, once data is lost and the ADV202 can not see a valid header input, it will output black fields until it detect a valid header again and continues decoding valid data.
If data is lost during a field, the information will be flushed from memory and the ADV202 waits for the next valid header while outputting black fields.
Do Vclk and Mclk have to be synchronous?
VCLK and MCLK can be of different sources and different frequencies. There is no requirement that VCLK and MCLK must be synchronous.
Exceptions are documented in the according release note for a particular part and can be found at:
How can I save on pin count or what is the absolute minimum pin connection required to make the ADV202/212 work?
Minimum pin requirements as listed will allow 16-bit Normal Host Mode for configuration and Host Interface Pixel Interface mode [HIPI mode] for data transfer of uncompessed and compressed data using both DMA channels.
DREQ0/ and DREQ1/
DACK0/ and DACK1/
How does the ADV202/212 synchronize to video input with HVF syncs?
ADV2x2 synchronization starts on the first active HSYNC edge after receiving the first inactive VSYNC edge.
The ADV2x2 requires HSYNC transitions on every line of active video and on blanking regions. The ADV202 and ADV212 share the same HSYNC syncing mechanism, but VSYNC synchronization on the ADV202 is different from the ADV212.
The ADV202 synchronizes to the VSYNC inactive edge only once. From then on it uses the HSYNC active edge and the dimension registers for synchronization.
For progressive video, the ADV212 synchronizes to every VSYNC inactive edge. For interlaced video, the ADV212 synchronizes to every Field1 VSYNC inactive edge.
How do I know when the ADV202/212 has finished compressing a field/frame/image?
In encode mode the LCODE signal on the SCOMM4 pin is used to indicate when the last word of the CODE FIFO is being read out.
SCOMM4/ LCODE is enabled by default and will assert [high] after the JPEG2000 EOC marker [0xFFD9]. For more detail on LCODE timing refer to:ADV202/212 Misc Appnotes
How can JPEG2000 be used in home video distribution?
JPEG2000 Enables Wireless HD Video Distribution in the Home
Does the ADV202/212 tile the input if my input image is larger than the maximum specified?
No. The user has to tile the input before compression if the input image size exceeds the maximum allowed image size of 1.048 Msamples/image.
Image width must stay below a maximum of 2048 samples or 4096 samples, depending which compression mode [5/3 or 9/7] is used. Refer to the datasheet for more detail on tile width limitations.
Can I use the ADV202/212 if my input is not to standard NTSC, PAL, 720p/60, 1080i/60 video?
Yes. If the input is to vary only in vertical and horizontal active and/or total resolution and is accompanied by HVF or EAV/SAV codes, Custom Specific mode can be used. In this mode the user defines active resolution and total resolution in writing to specific dimension registers.
Refer to the Programming Guide for details on Custom Specific Mode.
Why does 1080i/720p standard input require two ADV2x2s?
The data-input rate limits as specified in the datasheet refer to active resolution. Each ADV2x2 can handle a maximum of 65 Msamples.
1080i active resolution = 1920 x 1080 /2 x 60 = 62.208 Msamples/field/component. For YCbCr 4:2:2 input, this number is doubled, and 124.416 > 65, so two ADV2x2s are required.
Can I input RGB Bayer pattern directly to the ADV202/212?
No. The ADV202/212 only accepts YCbCr 4:2:2 component format or single component format.
What is the output format of the ADV202/212?
The ADV202/212 output is a JPEG2000 compatible compressed codestream file in either .j2c or .jp2 format.
Detailed description of the output format can be found in the JPEG2000 standard ISO/IEC 15444-1 and in the ADV202 technical note about the ADV202/212 output format at:ADV202/212 Output Format
A ADV202/212 generated file will contain a ADV202/212 generated 16-byte header at the start of each field/frame.
This header is required if the codestream is to be decoded by the ADV202/212 and must be removed if a different JPEG2000 decoder is used.
It is possible to output the ADV202/212 generated 16-byte header separately from the codestream. Refer to the ADV202/212 Programming Guide, Encode Parameter ATTRYPE.
Can I use JDATA mode in a multi-chip application?
Yes, if you use a 16-bit host configuration, you can use JDATA mode in a multi-chip application. However, the JDATA pins in a multi-chip application cannot be tied to each other. Refer to AN-796 for more information. In JDATA multi-chip mode, the BUSMODE and EDMODx registers must be set to JDATA mode.
Are there any artifacts on tile boundaries after merging tiles?
Generally tiles can be merged on boundaries without artifacts.
ADI provides a tile simulation software at:
Allows you to evaluate tile artifacts.
Are SCOMM4 and SCOMM5 required?
SCOMM5 is only required if synchronization of VDATA inputs or outputs is required when using more than one ADV202/212.
In this case, SCOMM5 of each ADV202/212 must be asserted by the host processor to start VDATA input or VDATA output.
SCOMM4 is optional. In encode mode SCOMM4 will assert when the last word is being read out of the CODE FIFO. In decode mode it will stay asserted as long as there is active video present in the Pixel Interface.
Can I stop/start encoding without reloading the firmware?
The STALLPAR parameter can be used to halt encoding momentarily by setting the STALLPAR parameter to its maximum value of 0xFF and back to 0x00 to start encoding again.
Can I input raw image data that comes from a high resolution still image source?
Yes. There are two methods to input raw image data to the ADV202:
- Over the VDATA bus using Raw Video Mode. This requires a synchronized pixel clock [Vclk] and HVF inputs along with the pixel data. HVF inputs are used in conjunction with the dimension register settings and define the image dimensions to be captured. Generally no horizontal or vertical blanking regions are expected with the input data. Refer to the ADV202/212 Programming Guide for Raw Video mode configuration.
- Over the HDATA bus. This requires the pixel data to be read into the part over the [up to] 32-bit interface that is also used for configuration of the part. Active region of image data to be captured is determined by register settings [XTOT, YTOT]. This interface is not synchronized to a pixel input clock. This mode is called Host Interface Pixel Interface mode [HIPI mode].
Maximum allowable image size is 1.048 Msamples/image. Images above this must be tiled prior to input to the ADV202/212.
What is visual weighting?
Visual weighting can be used for the lossy compression modes 9/7 or 5/3. Each visual weighting factor is used for a specific subband. Subband generation is explained in the article JPEG 2000 Image Compression and in the ISO/IEC 15444-1 standard.
Why are there two external DMA channels?
Generally only one DMA channel is used for compresed data input/output.
For Host Interface Pixel Interface [HIPI] mode both channels are used.
Channel 0 is used for uncompressed data input/output and channel 1 is used for compressed data output/input. When using HIPI mode it is recommended to use the DMA channels in a DMA burst configuration.
For more information refer to:ADV202 HIPImode Still Image Application
What parameters can I change on the fly?
Encode parameters that can be changed on a field-by-field basis:
STALLPAR, RCVAL, STEPSIZE and Visual Weighting.
Refer to the Programming Guide for more information how to use these encode parameters.