Frequently Asked Question
Why does spectral performance degrade when using larger values of multiplication on the clock multiplier?
The REF CLK multiplier is implemented by a PLL circuit. The phase noise performance of a PLL is determined by the multiplication ratio, and the loop filter performance. Within the loop bandwidth of the REF CLK multiplier, any noise that is present on the REF CLK will be gained up in proportion to the multiplication value (4x to 20x). This inherent effect degrades narrowband SFDR performance of the DDS, although it does not necessarily degrade the wideband SFDR. The formula for signal degradation within the PLL loop bandwidth is given by db = 20 log x, where x is the multiplication value. The loop bandwidth is typically a few hundred kHz.