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Frequently Asked Question

Why does the DDS spectral performance degrade when using large values of multiplication in the clock multiplier?

The REF CLK multiplier is implemented by a PLL circuit. The phase noise performance of a PLL is determined by the multiplication ratio and the loop filter performance. Within the loop bandwidth of the REF CLK multiplier, any noise that is present on the REF CLK will be amplified in proportion to the multiplication value. 4x to 20x multiplication is typical for ADI DDS devices. This inherent effect degrades narrow-band SFDR performance of the DDS; although it does not necessarily degrade the wideband SFDR. The formula for signal degradation within the PLL loop bandwidth is given by db = 20 log x, where x is the multiplication value. The loop bandwidth is typically a few hundred kHz and is also affected by the VCO charge pump current, which can easily be changed by programming it to a different value.