Product Details

DTS Symmetry for SHARC is an audio post-processing module developed by DTS Inc. for dynamically adjusting the audio gain to maintain the same level of perceived loudness for a stereo source without cause audible distortion. It is primarily designed for audio systems where the audio level of the source is highly variable.

Features

  • User configurable audio target level.
  • Built-in audio limiter minimizes distortions resulting from clipping.
  • Sampling rates supported: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1 and 48 kHz.
  • Frame size supported: any even frame sizes between 32 to 256 samples per channel.
  • Supports stereo input only.
  • Code compatible across the SHARC ADSP-214xx family of processors.
  • DTS certified on ADSP-21462/5/7/9, ADSP-21471/2/5/8/9, and ADSP-21481/2/3/5/6/7/8/9 processors.
  • Release format: Object code module with C source wrapper.
  • Input and output formats: non-interleaved multichannel 32-bit floating point samples.
  • No framework dependencies.

System Requirements

  • Windows XP Professional SP3 (32-bit only).
  • Windows Vista Business/Enterprise/Ultimate SP2 (32-bit only). It is recommended to install the software in a non-UAC-protected location.
  • Windows 7 Professional/Enterprise/Ultimate (32 and 64-bit).
  • Minimum of 2 GHz single core processor, 3.3 GHz dual core is recommended.
  • Minimum of 1 GB memory (RAM), 4 GB is recommended.
  • Minimum of 2 GB hard disk (HDD) space is required.
  • CrossCore® Embedded Studio for Analog Devices Processors
  • VisualDSP++ 5.0 for Analog Devices Processors and its latest update.
  • SigmaStudio Graphical Development Tools version 3.7 Build 7 or later.
  • SigmaStudio for SHARC Rel 2.0.0 or later.

Related Hardware

Performance Metrics

MIPS summary:

SHARC Processor Family Code memory (KiB) Data RAM (KiB) Constant Data Tables (KiB) MIPS
Average Peak
ADSP-2146x 8.43 4.97 0.95 15.9 16.2

  • MIPS measured using Fs = 48kHz, stereo input and output, optimal memory layout, running on a ADSP-21469.
  • Code compatible across all ADSP-214xx processors, with silicon anomaly workarounds implemented.
  • "Data RAM" for one instance, includes Stack, Scratch, Instance/State, Minimum Input and Output Single Buffers.
  • Both input and output buffer size used for data memory calculation is 256 bytes (utilizing a frame size of 32 samples per channel).
  • Frame size used for MIPS measurement is 256 samples per channel.

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Availability and Licensing

Each module supports the Analog Devices, Inc. (ADI) Blackfin or SHARC Processor family and is a licensed product that is available in object code format. Recipients must sign or accept a license agreement with ADI prior to being shipped or downloading the modules identified in the license agreement.

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