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G.711 Appendix I Voice Codec with PLC

G.711 Appendix I Voice Codec with PLC

Product
Details
System Requirements
Related Software
Related Hardware
Performance Metrics

Product Details

The “G.711 Appendix I Voice Codec with PLC” software library provides a combination of ITU-T G.711 voice codec and G.711 Appendix I packet loss concealment. G.711 is also known as a-law or µ-law encoding and decoding. This module operates at 8 kHz and is fully ITU compliant. It is typically used when communicating with a- and µ-law hardware codecs, in TDM trunks, or in VoIP when operating on G.711 RTP packets.

Features

API: C callable 'push'-type API
Compatible with Analog Devices Blackfin processor family
Rigorously tested
The module has no dependencies on processor peripherals or registers, adding greater system flexibility and ease of use
Conformance Standard: ITU-T Recommendation G.711 11/1988, ITU-T
Recommendation G.711 – Appendix I 9/1999
Target Processor: Code compatible across the Blackfin processor family ADSP-BF5xx
Framework Dependencies: None. No dependencies on processor peripherals or registers.
Release Format: Object code module with C source wrapper
Input and output buffer samples per block: 80
Sample Rate: 8 kHz
Bit Rate: 64 kbit/s
Multi-Channel: Fully re-entrant and multi-instancing capable

Product Download

Download Production Code (Rev. 1.0.2)

System Requirements

Windows XP Professional SP3 (32-bit only).
Windows Vista Business/Enterprise/Ultimate SP2 (32-bit only). It is recommended to install the software in a non-UAC-protected location.
Windows 7 Professional/Enterprise/Ultimate (32 and 64-bit). It is recommended to install the software in a non-UAC-protected location.

Minimum of 2 GHz single core processor, 3.3 GHz dual core is recommended.
Minimum of 1 GB memory (RAM), 4 GB is recommended.
Minimum of 2 GB hard disk (HDD) space is required.

Related Software

VisualDSP++ 5.0 and Latest Update

Related Hardware

Processor: ADSP-BF5xx, code compatible across the Blackfin processor family
Hardware: Evaluation board, for example ADSP-BF537 EZ-KIT Lite®

Performance Metrics

MIPS summary:

	Code RAM (KiB)	Data RAM (KiB)	Constant Data Tables (KiB)	MIPS
	Code RAM (KiB)	Data RAM (KiB)	Constant Data Tables (KiB)	BF533	BF548	BF527
Encoder	3.35	0.02	0.23	0.09	0.09	0.09
Decoder	3.35	2.60	0.23	0.14 (1.09 for PLC)	0.13 (1.08 for PLC)	0.13 (1.08 for PLC)

This table highlights example Blackfin processors and expected MIPS performance. Some processors include additional L2 internal memory (e.g. BF548) which can help reduce MIPS when fully utilized.
Similarly, processors with high speed external memory interfaces (32-bit versus 16-bit or DDR versus SDRAM) will also help reduce overall MIPS requirements.
MIPS were measured using optimal memory layout
ITU-T reference vector "sweep.src" is used for MIPS measurement
The MIPS for PLC is the maximum MIPS when packet loss concealment is executed
Both instruction and data cache have been enabled and data cache was set to write-back mode
"Data RAM" refers to a single instance and includes stack, scratch and instance/state memory as well as minimum-size input and output single buffers
1 KiB = 1024 Bytes

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Availability and Licensing

Each module supports the Analog Devices, Inc. (ADI) Blackfin or SHARC Processor family and is a licensed product that is available in object code format. Recipients must sign or accept a license agreement with ADI prior to being shipped or downloading the modules identified in the license agreement.