Product Details

TIFF is a lossless decoder which can be used as a contained for archiving. The implementation is highly optimized for Analog Devices ADSP-BF5xx Blackfin processors. This release will work on image cached from L3 memory. It is a self-contained software component that has been rigorously tested. It contains an intuitive C-callable API that is interruptible, maintains flexibility and provides seamless system integration.

Features

  • Cache: Both instruction and Data cache enabled
  • Code compatible across the Blackfin Processor Family ADSP-BF5xx
  • MISRA-C compliant
  • Target Processors : ADSP-BF561, ADSP-BF533, ADSP-BF527, ADSP-BF548
  • Release format : Object Code with source code wrapper
  • Input format : TIFF
  • Output format : RGBA
  • Image size : Configurable
  • Multi instancing : Fully re-entrant and multi-instance capable

System Requirements

  • Windows XP Professional SP3 (32-bit only).
  • Windows Vista Business/Enterprise/Ultimate SP2 (32-bit only). It is recommended to install the software in a non-UAC-protected location.
  • Windows 7 Professional/Enterprise/Ultimate (32 and 64-bit). It is recommended to install the software in a non-UAC-protected location.
  • Minimum of 2 GHz single core processor, 3.3 GHz dual core is recommended.
  • Minimum of 1 GB memory (RAM), 4 GB is recommended.
  • Minimum of 2 GB hard disk (HDD) space is required.

Related Hardware

  • Processor: BF52x, BF53x, BF54x, BF561 processor families.Demonstration applications provided to run on ADSP-BF527or ADSP-BF533 or ADSP-BF548 or ADSP-BF561 EZ-KIT Lite.

Hardware: One of the following development hardware combinations

Performance Metrics

 MIPS summary:

  Memory (Bytes) Performance
Module Image Width Image Height Code Stack Data RAM Data ROM Average Cycles / pel MIPS
Decode TIFF (Uncompressed RGB) 225 65 24984 432 40952 972 43.26 9.49
Decode TIFF (LZW RGB) 512 512 22148 492 40952 972 402.04 1580.90

  • Performance (average cycles per pel) measured on ADSP-BF533. The code and data are cached from L3 memory
  • MIPS is measured as ((cycles/pel) * (image width) * (image height) * (frames/second) / 10^6). (It is assumed that frames/second = 15 for calculation)
  • Code compatible across all ADSP-BF5xx processors, with silicon anomaly workarounds implemented based on the following boards.
  • "Data RAM" for one instance, includes Scratch and Instance/State. Input buffer size is 2 KiB and output buffer size is 1 KiB

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Availability and Licensing

Each module supports the Analog Devices, Inc. (ADI) Blackfin or SHARC Processor family and is a licensed product that is available in object code format. Recipients must sign or accept a license agreement with ADI prior to being shipped or downloading the modules identified in the license agreement.

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