Flexible LVDS interface allows word, byte, or nibble load
Single-carrier W-CDMA ACLR = 82 dBc @ 122.88 MHz IF
Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω
Novel 2×/4×/8× interpolator/complex modulator allows carrier placement anywhere in the DAC bandwidth
Digital gain and phase adjustment for sideband suppression
Multiple chip synchronization interfaces
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
Low power: 1.5 W @ 1.2 GSPS, 800 mW @ 500 MSPS, full
operating conditions
72-lead, exposed paddle LFCSP