Broadband 6 GHz Active Mixer with a Glueless Local Oscillator Interface
This circuit offers an optimum solution that is attractive in wideband applications that require frequency conversion to higher or lower frequencies. The two-chip circuit covers a broad LO frequency range from 35 MHz to 4400 MHz. The LO interface is simple and glueless, eliminating the need for a balun, matching network, and LO buffer. In addition, the mixer bias adjust function allows optimization of IP3, noise figure, and supply current based on the application requirements or on the size of the input signal.
The ADL5801 is a high linearity, double balanced, active mixer with an integrated LO buffer amplifier that supports RF frequencies from 10 MHz to 6000 MHz. The mixer has a bias adjust feature to optimize the input linearity, noise figure and dc operating current. The circuit shown in Figure 1 has a simple LO interface for applications that require broadband up or down conversion. The interface provides coverage for RF frequencies ranging from 35 MHz to 4400 MHz.
The ADF4351 PLL has a differential LO output interface, and the ADL5801 is optimized for differential LO drive. Differential interfaces provide common-mode noise rejection and cancellation of even order harmonics.
Normally, pull-up bias inductors are recommended at the output port of the ADF4351. This solution delivers higher output power but limits the frequency range of the device. The standard evaluation board is equipped with two 7.5 nH pull-up inductors, which is optimal for frequencies above 500 MHz. In the Figure 1 circuit, the bias inductors are replaced with two-50 Ω pull-up resistors to reduce the frequency dependence of the output interface. This change results in lower power delivered at the output; however, the ADL5801 can tolerate this limitation since the device is specified to operate at LO drive levels as low as −10 dBm. Figure 2 is a comparison of the output power delivered by the device with resistive and inductive pull-up networks.
The resistive pull-up network presents a nominal differential impedance of 100 Ω at the output, and the differential input impedance of the LO port of the ADL5801 is 50 Ω. The impedance mismatch in the LO path of the mixer does not degrade the circuit performance. However, it is suggested that the length of the traces connecting the devices be kept as short as possible to minimize effects of the impedance mismatch.
The PLL-mixer interface described above exhibits excellent broadband performance as shown in Figure 3 and Figure 4. The circuit maintains an input IP3 of more than 25 dBm at frequencies below 3500 MHz, and 23 dBm up to 4400 MHz. The circuit exhibits conversion gain of more than −0.7 dB and noise figure less than 12.2 dB across the operating frequency band.
The power consumed by the circuit depends on the frequency of operation and the mixer’s bias point. The ADF4351 activates a combination of sections in its divider network to generate output frequencies that span multiple octaves. This combination dictates the power consumption of the PLL. For example, when the PLL is programmed to output a frequency of 35 MHz, the device activates all six divider networks and consumes 132 mA of current. This point represents the worst-case power consumption point for the device. Similarly, the bias level of the ADL5801, which can be used to adjust IP3 and noise figure, determines the power consumed by the mixer. The VSET pin is used to adjust the bias level of the device. Figure 5 and Figure 6 show the dc current, input IP3, and noise figure performance of the mixer as a function of the VSET voltage.
The VSET level is directly proportional to the dc operating current and input IP3, while the noise figure is inversely proportional to the VSET voltage. The mixer exhibits the best linearity at a VSET voltage of 3.6 V. At a mixer bias level of 3.6 V and the worst-case power consumption point for the PLL (all dividers on), the circuit consumes approximately 1.14 W.
Table 1 and Table 2 list components modified on the evaluation boards to implement this applications circuit.
Table 1. Component Modifications on EVAL-ADF4351EB1Z
|Placeholder||Default Value||New Value|
|L2, L3||7.5 nH||50 Ω|
|L1, L4||1.9 nH||0 Ω|
Table 2. Component Modifications on EVAL-ADF4351EB1Z
|Placeholder||Default Value||New Value|
|T2/T4/T7||Mini-Circuits TCM1-1-13M+||0 Ω|
|C4, C5||100 pF||1 nF|
Figure 8 shows a block diagram of the test setup. The output of the PLL and the LO port of the mixer were bridged using a coaxial thru connector for evaluation. Figure 7 shows a photo of the two connected evaluation boards. The following is a list of equipment used to evaluate the circuit.
- Windows® XP, Windows® Vista (32-bit), or Windows® 7 (32-bit) PC with USB port
- ADF4351 evaluation board (EVAL-ADF4351EB1Z)
- ADL5801 evaluation board (ADL5801-EVALZ)
- RF Signal generator (Rohde & Schwarz SMT06 or equivalent)
- Spectrum analyzer (Rohde & Schwarz FSEA30 or equivalent)
- Power supplies: Agilent E3631 or equivalent
EVAL-ADF4351EB1Z: +5.5 V
ADL5801-EVALZ: +5 V (VPOS), +3.6V (VSET)
The control software was used to program the desired LO frequency and the output power. Figure 9 is a sample screen shot of the software configuration used to drive the ADF4351. See UG-435 User Guide, Evaluation Board for the ADF4351 Fractional-N PLL Frequency Synthesizer and UG-476 User Guide, PLL Software Installation Guide for further information on setting up the ADF4351.
The ADL5801 was biased with a VSET voltage of 3.6 V using an external power supply. This external bias connection can be replaced with an on-board connection routed through the supply pin using a resistive divider network. Populating placeholder R10 and leaving R7 and R8 open enables this resistive divider network. Table 3 provides the value of R10 required to achieve desired mixer bias level. For additional information, refer to the “RF Voltage-to-Current (V-to-I) Converter” section in the ADL5801 datasheet.
Table 3. Suggested Values of R10 to Achieve the Desired Mixer Bias Level (IPOS is the Corresponding ADL5801 Supply Current)
|R10 (Ω)||VSET (V)||IPOS (mA)|
To demonstrate the circuit’s capability to support RF frequencies from 35 MHz to 4400 MHz, the device was operated in a high side LO configuration with an IF frequency of 153 MHz.