High Voltage (30 V) DAC Powered from a Low Voltage (3 V) Supply Generates Tuning Signals for Antennas and Filters
The circuit shown in Figure 1 generates a high voltage signal that controls the capacitance of a BST (barium strontium titanate) capacitor. The capacitance of a BST capacitor can be altered by applying a voltage of between 0 V and 30 V to the correct terminal. This changes the thickness of the dielectric and, hence, the capacitance. BSTs are often used for tuning antenna arrays or tunable filters. Clearly, there is an advantage in being able to tune these applications—for example, compensating for component tolerance errors, fine tuning the cutoff frequency of a filter, or network impedance matching for tunable antennas.
This application requires a convenient, compact, and low cost circuit to generate the high voltage power supply because it is often not practical to add a separate supply simply for this function alone. The circuit in Figure 1 meets these requirements using the ADP1613 boost converter and the AD5504 30 V/60 V DAC. Total board area for the boost regulator circuit is only 43 mm2. The ADP1613 is available in an 8-lead MSOP package and the AD5504 in a 16-lead TSSOP.
The boost circuit can also be used in LED driver applications and to supply receiver bias voltages in optical communications systems.
Figure 1. Boost Supply and High Voltage DAC Provide Tuning Signal for BST Capacitors (Simplified Schematic: All Connections Not Shown)
The circuit has a 3 V (VDD) power supply available, and the BST capacitors require voltages in excess of 20 V for full control. The two main circuit blocks are the ADP1613 step-up switching converter and the AD5504 high voltage DAC. The circuit diagram is shown in Figure 1.
The ADP1613 is a step-up dc-to-dc switching converter with an integrated power switch capable of providing an output as high as 20 V. Using additional external components, higher voltages can be achieved. The ADP1613 has an adjustable soft start function to prevent inrush current when the device is enabled. The pin-selectable switching frequency and PWM current mode architecture allows easy noise filtering and yields excellent transient response. The components connected around the ADP1613 generate a 32 V output from a 3 V input.
The ADIsimPower™ design tool provides an easy way for designers to determine the appropriate components based on input and output requirements. The design of the ADP1613 circuit shown in Figure 1 uses the "lowest cost" option of ADIsimPower with an input voltage of 3 V, output voltage of 32 V, and a load current of 40 mA. The design can be downloaded at www.analog.com/CN0193-PowerDesign.
The ADIsimPower design file includes the bill of material, detailed schematic, bode plots, efficiency plots, transient response, as well as a suggested board layout.
The 32 V output from the ADP1613 is used as the power supply for the AD5504. The AD5504 is a quad channel, 12 bit DAC capable of an output voltage up to 60 V. The full-scale output of the AD5504 is determined by the state of the R_SEL pin. In this application, R_SEL is connected to VDD, selecting a full-scale output of 30 V. The AD5504 is controlled by a serial interface, which is compatible with 3 V logic. The DAC outputs are changed by writing to the appropriate DAC registers via the serial interface. The DACs can be updated simultaneously by pulsing the Load DAC (LDAC) pin low, thus allowing for all four BST capacitors to be changed at the same time.
Using the circuit shown in Figure 1, it is possible to generate DAC output voltages up to 30 V. The output voltages are used to set the bias voltage for BST capacitors, which, in turn, adjust the antenna response. Figure 2 shows the equivalent circuit of a BST capacitor used as a tunable matching network, and Figure 3 shows the transfer function of the BST capacitance as a function of bias voltage and the resulting antenna response. More information on BST capacitors can be found at www.agilerf.com.
In any circuit where accuracy is important, it is important to consider the power supply and ground return layout on the board. The printed circuit board (PCB) containing the circuit should have separate analog and digital sections. If the circuit is used in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5504. The circuit should be constructed on a multilayer PCB with a large area ground plane layer and a power plane layer. See MT-031 Tutorial for more discussion on layout and grounding.
The power supply to the AD5504 should be bypassed with 10 μF and 0.1 μF capacitors. The capacitors should be as physically close as possible to the device, with the 0.1 μF capacitor ideally right up against the device. The 10 μF capacitor should be either the tantalum bead type or ceramic type. It is important that the 0.1 μF capacitor have low effective series resistance (ESR) and low effective series inductance (ESL), such as is typical of common ceramic types of capacitors. This 0.1 μF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. See MT-101 Tutorial for more details on proper decoupling techniques.
The power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground.
The ADIsimPower design file shows a recommended layout for the ADP1613 portion of the circuit. The file can be downloaded at www.analog.com/CN0193-PowerDesign. A complete design support package for this circuit note can be found at www.analog.com/CN0193-DesignSupport.
Figure 3. Bias Voltage vs. BST Capacitance, and Resulting Antenna Response
The circuit of Figure 1 is tested by applying a 3 V power supply to VDD. This creates a 32 V supply for the AD5504 (measurable on Pin 14) and also supplies the VLOGIC supply for the AD5504. A microcontroller, DSP, or FPGA is used to provide the appropriate digital interface signals to the AD5504.
For normal operation CLR should be high. The SYNC, SCLK, and SDATA lines should be operated as described in the AD5504 data sheet to write data to the various registers of the AD5504. When data is written to a DAC register with LDAC low, the appropriate output will update immediately. When data is written to a DAC register with LDAC high, the DAC output will remain at its current value until LDAC is pulsed low.