Features & Benefits
- Automated calibration technique
- Offset voltage less than 1 mV
- Common industrial voltage output levels
Circuit Function & Benefits
The AD5360 is factory trimmed to have a very low offset. The trimming is done with the offset DAC at its default value, and the offset error due to the offset DAC is effectively removed. When the value of the offset DAC is changed from its default value, however, its offset error affects the offset error of the main DACs.
The circuit described here allows for the offset error of the main DACs to be measured and calibrated out under those conditions. The circuit relies on a general-purpose I/O pin and an on-chip monitor multiplexer. The GPIO (general-purpose I/O) pin is set as an input, and by reading the GPIO internal register, the logic status of the GPIO pin is determined. The analog multiplexer is programmable to connect any of the 16 DAC outputs to a single pin, the MON_OUT pin. The multiplexer switches have a low but finite on resistance, RON so that any current drawn from MON_OUT creates a voltage drop across RON and, therefore, an output error. To prevent this, MON_OUT is buffered by an AD8597 low-noise amplifier. The low pass filter following the amplifier reduces the amount of noise seen by the AD790 high speed precision comparator and prevents false triggering.
The AD790 can be operated on ±15 V supplies, making it compatible with the AD5360. The AD790 also requires an additional +5 V VLOGIC supply when operating on ±15 V supplies. In addition, the AD790 has a 15 V maximum differential input voltage; therefore, it can tolerate the output voltages from the AD5360 without attenuation. In Figure 1, the comparator output is low if the channel offset is positive, indicating that the output voltage must be reduced to remove the offset. The comparator output is high if the channel offset is negative, indicating that the output voltage must be increased to remove the offset.
To calibrate a DAC, the DAC channel is loaded with the digital value, which should ideally provide a voltage equal to SIGGND (that is, 0 V). In this example the DAC channel is assumed to have a negative offset. Reading the GPIO register shows that the comparator output is low, indicating that the input must be incremented until the output toggles. As progressively higher codes are written to the DAC input register, the GPIO register is read until the comparator trips to the high state. The AD790 has a maximum hysteresis band of 0.65 mV; therefore, reducing the DAC code again allows a more accurate determination of the DAC offset.
When comparator output trips back to the low state, SIGGND is somewhere between those two codes. Due to the errors of the components used in the circuit, there is typically a span of three or four codes between comparator trip points. There is no way to determine exactly which code gives the lowest offset output using this method, but by picking a code that is the average of the two trip point codes, the DAC channel offset is typically less than 1 mV from SIGGND.
Excellent layout, grounding, and decoupling techniques must be used to achieve the desired performance from the circuits discussed in this note (see MT-031 Tutorial and MT-101 Tutorial). As a minimum, a 4-layer PCB should be used with one ground plane layer, one power plane layer, and two signal layers.
The circuit described here can be used with any of the AD536x devices mentioned above. The reference can also be changed to give different output ranges if required.
|AD5360||16-Channel, 16-Bit, Serial Input, Voltage-Output DAC|
|AD790||Fast, Precision Comparator||
|AD8597||Ultralow Distortion, Ultralow Noise Op Amp (single)||
|ADR435||Ultralow Noise XFET® Voltage References with Current Sink and Source Capability||