DC-Coupled, Single-Ended-to-Differential Conversion Using the AD8138 Low Distortion Differential ADC Driver and the AD7352 Dual, 3 MSPS, 12-Bit SAR ADC
Figure 1: AD8138 Single Ended to Differential Conversion Driving the AD7352 Differential Inputs
If the analog inputs source being used has zero impedance, all four resistors (RG1, RG2, RF1, and RF2) should be the same as shown in Figure 1. If the source has a 50 Ω impedance and a 50 Ω termination, for example, the value of RG2 should be increased by 25 Ω to balance this parallel impedance on the input and thus ensure that both the positive and negative analog inputs have the same gain. This also requires a small increase in RF1 and RF2 to compensate for the gain loss caused by increasing RG1 and RG2. Complete analysis for the terminated source condition is found in the ADIsimDiffAmp interactive design tool and in MT-076 Tutorial.
The AD7352 requires a driver that has a very fast settling time due to the very short acquisition time required to achieve 3 MSPS throughput with a serial interface. The track-and-hold amplifier on the front end of the AD7352 enters track mode on the rising edge of the 13th SCLK period during a conversion. The ADC driver must settle before the track-and-hold returns to hold (68 ns later for 3 MSPS throughput on the AD7352 using a 48 MHz SCLK). The AD8138 has a specified 16 ns settling time that satisfies this requirement.
The voltage applied to the VOCM pin of the AD8138 sets up the common-mode voltage. In Figure 1, VOCM is connected to 1.024 V, which is a divided version of the internal 2.048 V reference on the AD7352. If the on-chip 2.048 V reference on the AD7352 is to be used elsewhere in a system (as illustrated in Figure 1), the output from REFA or REFB must first be buffered. The OP177 features the highest precision performance of any op amp currently available and is a perfect choice for a reference buffer.
Note that the AD8138 operates on dual 5 V supplies whereas the AD7352 is specified for power supply voltages of 2.5 V to 3.6 V. Care must be taken to ensure that the input maximum input voltage limits of the AD7352 are not exceeded during transient or power-on conditions (see MT-036 Tutorial). In addition, the circuit must be constructed on a multilayer PC board with a large area ground plane. Proper layout, grounding, and decoupling techniques must be used to achieve optimum performance (see MT-031 Tutorial, MT-101 Tutorial, and the AD7352 evaluation board layout).