S/PDIF and I2S Interface for a SigmaDSP Codec Using the ADAV801/ADAV803 Audio Codec
The audio input in S/PDIF format is converted to I2S before processing by the ADAU1761, and the processed audio output in I2S format is converted back to S/PDIF by the ADAV801/ ADAV803. The ADAV801/ ADAV803 has a flexible digital input/output routing matrix that allows it to process audio in either I2S or S/PDIF format and output it in either format as a master or slave with the use of an onboard SRC (sample rate converter). The ADAV801/ ADAV803 support the consumer audio standard, and channel status data can be embedded in the audio stream by writing to the relevant registers in the ADAV801/ ADAV803. This is a useful feature for passing configuration information between devices. The ADAV801/ ADAV803 has a stereo DAC/ADC that can also be used to process audio as needed.
Figure 1. ADAV801/ADAV803 Connections for S/PDIF In/Out to ADAU1761 SigmaDSP (Simplified Schematic: Power Supply Decoupling and All Connections Not Shown)
The S/PDIF input comes from the TORX173 fiber optic
receiver module into the DIRIN pin and is then output to the
ADAU1761 on the record port in I2S format. Once the audio is
processed by the ADAU1761 SigmaDSP® device it is output on
the ADC_SDATA pin to the playback port of the ADAV801/
ADAV803 in I2S format. It is then converted to S/PDIF format
on the DITOUT pin and fed to the TOTX173 fiber optical
The circuit is powered from a 3.3 V AVDD supply. The master clock for the circuit is generated either by the ADAV801/ ADAV803 or by an external oscillator, depending on whether the ADAU1761 is to be configured as master or slave. In the case where the ADAU1761 is a slave, i.e. the BLCK and LRCLK are driven by the ADAV801/ ADAV803, the MCLK is 256× the recovered audio clock from the S/PDIF stream. It can also be configured to be 512× the recovered clock. This clock is accessed on the SYSCLK3 pin of the ADAV801/ ADAV803 and connected to the MCLK pin of the ADAU1761.
When the ADAU1761 is master, the MCLK is generated by an
onboard oscillator and is supplied to the ADAV801/ADAV803
on the MCLKI pin. In this case, the ADAU1761 drives the
LRCLK and BCLK lines, and the SRC on the ADAV801/ADAV803 is used to synchronize the audio between the I2S port
and the S/PDIF port.
A complete design support documentation package for this circuit note can be found at www.analog.com/CN0219-DesignSupport. This includes register setting files for both master and slave configuration for the ADAV801/ADAV803 and ADAU1761. These register settings files can be loaded using the relevant evaluation board software.
The ADAU1761 evaluation board is programmed using SigmaStudio thru a USBI board (EVAL-ADUSB2EBZ). The SigmaStudio GUI software requires a PC with the following: Windows® 7, Windows Vista, or Windows XP Professional or Home Edition with SP2, 128 MB of RAM (256 MB recommended), 50 MB of available hard disk space, 1024 × 768 screen resolution, and USB 1.1/2.0 data port. The ADAV801/ ADAV803 board is controlled using the printer port of a PC with its own software that can be downloaded from the ADI website. Two optical connectors are needed to connect the S/PDIF input/output to the ADAV801/ ADAV803 board. Eight single pin jumper cables are needed to make the necessary connections between the two evaluation boards.
From this point, follow the documentation for the EVAL-ADAU1761Z and EVAL-ADAV801/ EVAL-ADAV803EBZ regarding software installation, setup, and operation of the system.
The SigmaStudio software is used to program and tune the registers and SigmaDSP core in the ADAU1761. SigmaStudio can be downloaded from www.analog.com/sigmastudio.
The software for the ADAV801/ ADAV803 can also be downloaded from the ADI website. Once the software is installed, the register setting files in the design documentation can be loaded to program both boards depending on whether you want the ADAU1761 device to be master or slave. The ADAU1761 SigmaStudio project has just a simple audio passthru with volume control for the purposes of testing the circuit of Figure 1.
Figure 3. Functional Diagram of Test Setup
Setup and Test
An Audio Precision APx585 multichannel audio analyzer can be used to generate the S/PDIF input and capture the S/PDIF output. With the ADAU1761 as master and a full-scale 1 kHz input tone, the THD + N should be ~130 dB at the S/PDIF output. In slave mode, the THD + N should be ~142 dB, since there is no SRC needed to synchronize the S/PDIF stream to the ADAU1761 I2S stream.