High Frequency Variable Gain Amplifier Extends the Dynamic Range of a 10-Bit, 65 MSPS ADC to Greater Than 100 dB
Variable gain amplifiers (VGAs) serve a critical function when an analog signal with wide dynamic range is converted to digital format, and the ADC resolution is insufficient to capture all useful information. For example, a 10-bit converter with a 2 V p-p input range has an LSB weight of 2 ÷ 1024, or just under 2 mV.
Figure 1: Interconnecting an AD8331 VGA and an AD9215 ADC (Simplified Schematic, All Connections/Decoupling Not Shown)
This represents a dynamic range of approximately 60 dB. A wideband VGA can be used ahead of the ADC to amplify input signals with amplitudes less than the minimum resolution and attenuate large signals that would otherwise saturate the ADC.
Examples of such applications are ultrasound receivers where the signal strength ranges from microvolts to several volts, and the intermediate frequency (IF) amplifier used in virtually all receivers. For dc or low frequency analog signals, Σ-Δ ADCs with resolutions up to 24 bits are economical and plentiful, but typically limited in sampling frequency to a few hundred kilohertz. State-of-the-art, available ADC resolution decreases as sampling frequency increases. This makes accurate digitization of high frequency, low amplitude signals extremely difficult using standard ADCs.
Variable gain amplifiers are a convenient solution to this problem. The AD8331/AD8332/AD8334 are single-, dual-, and quad-channel, ultralow noise, linear-in-dB, variable gain amplifiers (VGAs). Optimized for ultrasound systems, they are usable as a low noise variable gain element at frequencies up to 120 MHz.
Included in each channel are an ultralow noise preamp (LNA), an X-AMP® VGA with 48 dB of gain range, and a selectable gain postamp with adjustable output limiting. The LNA gain is 19 dB with a single-ended input and differential outputs. Using a single resistor, the LNA input impedance can be adjusted to match a signal source without compromising noise performance.
The 48 dB gain range of the VGA makes these devices suitable for a variety of applications. Excellent bandwidth uniformity is maintained across the entire range. The gain control interface provides precise linear-in-dB scaling of 50 dB/V for control voltages between 40 mV and 1 V. Factory trim ensures excellent part-to-part and channel-to-channel gain matching.
The circuit shown in Figure 1 demonstrates the interconnection of a typical VGA and ADC. For this example, the AD8331 VGA and AD9215 ADC are compatible in frequency range and differential interface matching. For clarity, power supply decoupling is omitted from the figure.
The AD8331 includes a low noise preamplifier, followed by a differential attenuator and gain stages. This VGA requires only a single 5 V power supply. Low noise 3 V for the ADC can be provided by an LDO, such as the ADP3339, which is connected to the 5 V supply. The differential output of the VGA is designed to drive ADCs with differential inputs over a wide range of devices from 1 V p-p to about 4.5 V p-p. The input range of the AD9215 can be set between 1 V p-p differential and 2 V p-p differential. For this circuit, the ADC input range was set to 2 V p-p differential.
As with most single-supply devices, the AD8331 requires an internal mid-supply reference for a pair of mirrored amplifiers that provide equal but opposite polarity signals at the output referenced to the common-mode voltage (CMV). Consult the AD8331 data sheet for further information regarding this function. Pin 11 (VCM) of the VGA functions as both an input and an output. As an output, the VCM circuit is available for dc coupling at Pin 11, or the pin can be driven from a voltage source to modify the value of the common-mode voltage to accommodate ADCs with various input ranges. Left floating, the VCM voltage is one-half the supply voltage, which is optimum for ac-coupled applications.
Pin 12, CLMP, clamps the output swing within the limits of the differential inputs of the ADC, thereby avoiding overdrive, which can be a serious problem with converters. A simple resistor controls the clamp amplitude. If no connection is made to the CLMP pin, the clamp voltage is 4.5 V p-p differential centered on a common-mode voltage of 2.5 V.
A 1 MHz sinewave was selected for the test waveform, and a recovered waveform from the ADC Analyzer™ software is shown in Figure 2. The sampling frequency was 65 MSPS, corresponding to the 65 MSPS version of the AD9215.
The LNA input signal was 70 mV p-p, following external low-pass and high-pass filters to reject signal generator spurs. The VGA gain was 29 dB, amplifying the signal to about one-half the ADC full-scale input voltage. Combined high-pass and low-pass filtering between the VGA and the ADC attenuates low frequency noise below 50 kHz (33 Ω and 100 nF yield a low frequency cutoff frequency of 48 kHz) and frequencies above 100 MHz (42 pF and 33 Ω yield a high frequency cutoff frequency of 114 MHz).
Additional high-pass filtering is possible by reducing the value of the series capacitor at the LNA input and the series capacitors between the LNA and VGA inputs.
Figure 2: Reconstructed Full-Scale 2 VP-P 1 MHz Sinewave, Sampling Rate = 65 MSPS
An output decoupling network, consisting of a fixed 100 Ω resistor in parallel with a ferrite bead inserted in series with each AD8331 output, may be required if there is more than approximately 25 pF stray PCB trace capacitance on VOH and VOL. Otherwise, the network is not required.
Most modern ADCs provide pin access to the internal reference. For the AD9215, the internal reference voltage is 1 V, and external resistors bias the common-mode input voltage at one-half the 3 V supply.
The data capture board interfaces to a laptop computer. The ADC Analyzer software enables the converter and provides waveform or FFT displays. For the AD9215, consult the AD9215 data sheet for the configuration details.
Figure 3 is a simplified block diagram of the test setup. A 20-pin, dual-row header mounted to the evaluation board mates to half of the connector on the converter interface board. The board is controlled using ADC Analyzer software running on a standard laptop PC.
The circuit must be constructed on a multilayer PC board with a large area ground plane. Proper layout, grounding, and decoupling techniques must be used to achieve optimum performance (see MT-031 Tutorial, Grounding Data Converters and Solving the Mystery of AGND and DGND and MT-101 Tutorial, Decoupling Techniques).
A complete design support package for this circuit note can be found at http://www.analog.com/CN0096-DesignSupport.
Figure 3: Block Diagram Showing Test Configuration
Windows® XP, Windows Vista (32-bit), or Windows 7 (32-bit) PC with USB port, AD8331ARU-VGA-ADC, HSC-ADC-EVALB-DCZ evaluation boards, and the AD9215 evaluation software, power supplies, spectrum analyzer, signal source. See user guide UG-173 and the AD8331 and AD9215 data sheets for additional details.
See user guide UG-173 for the HSC-ADC-EVALB-DCZ data capture evaluation board operation and installation of the ADC Analyzer software. See Figure 1 of this circuit note for the block diagram, "AD8331ARU-VGA-ADC-SCH-Rev0.pdf” for schematics, AD8331ARU-VGA-ADC-AssemblyDrawing-RevA.pdf, and the “AD8331ARU-VGA-ADC-BOM-Rev0.pdf” for the bill of materials.
Functional Block Diagram
See user guide UG-173 and Figure 1 of this circuit note for the circuit block diagram. Also see file “AD8331ARU-VGA-ADC-SCH-Rev0.pdf” for the schematics.
Setup and Test
See Circuit Description section for setup and test details and user guide UG-173 for the HSC-ADC-EVALB-DCZ data capture evaluation board. UG-173 describes the board operation, and installation of the ADC Analyzer software. Also see Figure 1 of this circuit note for the block diagram.
|AD9411||10-Bit, 170/200 MSPS 3.3 V A/D Converter|
|AD8331||Single VGA with Ultralow Noise Preamplifier and Programmable RIN|
|AD9215||10-Bit, 65/80/105 MSPS 3 V A/D Converter|
|AD9214||10-Bit, 65/80/105 MSPS, +3.3V A/D Converter|