Dolby Pro Logic IIx Decoder, SHARC

The Dolby Pro Logic IIx library for the SHARC processor is a proprietary algorithm from Dolby Laboratories intended for extending stereo or 5.1-channel audio to 6.1 or 7.1 channels.
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  • Input format: 32-bit floating-point (range -1 to 1). Input PCM must be provided in separate buffers for each channel.
  • Output format: Single channel 32-bit floating-point. Output PCM will be provided in a buffer for single channel.
  • Output buffer samples per block: Configurable and dependent upon input block size (7 * X, where X is input block size).
  • Sample Rate: All sampling frequencies specified by Dolby Pro Logic IIx specifications (32, 44.1, 48, 64, 88.2, 96 kHz).
  • Block Size: Minimum of 8 samples.
  • Delay Algorithmic: Delay is nominally 5ms.
  • Release format: Object code module.
  • API: C callable 'push' API.
  • Code compatible across the SHARC ADSP-2136x Processor Family and ADSP-214xx Processor Family.
  • Framework dependencies: None.
  • Multi-instancing: Fully re-entrant and multi-instance capable.
  • Conformance Standard: Dolby compliance/certification for DPLIIx.
  • Certified processors: ADSP-21362/3/4/5/6, ADSP-21367/8/9, ADSP-21462/5/7/9, ADSP-21471/2/5/8/9, ADSP-21481/2/3/5/6/7/8/9.

Product Details

Dolby® Pro Logic IIx (DPLIIx) is a proprietary algorithm from Dolby Laboratories intended for extending stereo or 5-channel audio to 6 or 7 channels. DPLIIx uses matrix surround decoding technology to create an extended-channel surround sound playback experience. DPLIIx has applications in home and car entertainment systems, PC audio, games consoles, and others. DPLIIx has three different listening modes which allow users to tailor audio reproduction to different types of audio programs


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Each module supports the Analog Devices, Inc. (ADI) Blackfin or SHARC Processor family and is a licensed product that is available in object code format. Recipients must sign or accept a license agreement with ADI prior to being shipped or downloading the modules identified in the license agreement.

Performance Metrics

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MIPS /Memory summary:

 SHARC Processor
 Code RAM (KiB)   Data RAM (KiB)   Constant Data Tables (KiB)  MIPS

  • MIPS measured using Fs = 44.1 kHz, optimal memory layout, worst case test vector, stereo input and 7-channel output.
  • "Data RAM" for one instance, includes Stack, Scratch, Instance/State, two single-buffered input buffers and seven single-buffered output buffers.
  • Input buffer size is 2048 bytes and output buffer size is 7168 bytes, all storing 32-bit floating-point samples.
  • Frame size considered is 256 samples per channel.
  • Reduced code size for ADSP-214xx is due to the short-word instruction mode available for this processor family

Systems Requirements

  • Windows XP Professional SP3 (32-bit only).
  • Windows Vista Business/Enterprise/Ultimate SP2 (32-bit only). It is recommended to install the software in a non-UAC-protected location.
  • Windows 7 Professional/Enterprise/Ultimate (32 and 64-bit). It is recommended to install the software in a non-UAC-protected location.
  • Minimum of 2 GHz single core processor, 3.3 GHz dual core is recommended.
  • Minimum of 1 GB memory (RAM), 4 GB is recommended.
  • Minimum of 2 GB hard disk (HDD) space is required.
  • CrossCore® Embedded Studio for Analog Devices Processors.

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