Dolby® Pro Logic IIz Decoder
- Code base origin: Dolby Pro Logic IIz Implementation kit, Issue 1.0.
- Compliance: Dolby test/certification requirements for Dolby Pro Logic IIz.
- Framework dependencies: None. No dependencies on processor peripherals or registers.
- Certified processors: ADSP-21362/3/4/5/6, ADSP-21367/8/9, ADSP-21462/5/7/9, ADSP-21471/2/5/8/9, ADSP-21481/2/3/5/6/7/8/9.
- API: C callable 'push' API.
- Release Format: Object libraries for Dolby Pro Logic IIx and Dolby Pro Logic IIz, source code for the post-processing functions additional to Dolby Pro Logic IIx.
- Input format: 32-bit floating-point ranging from -1.0 to 1.0, two channels, non-interleaved.
- Output format: 32-bit floating-point ranging from -1.0 to 1.0, up to 7 channels, non interleaved.
- Output buffer samples per block: Configurable and dependent upon input block size (7 * X, where X is input block size).
- Sample Rates: 32, 44.1, 48, 64, 88.2 and 96 kHz.
- Output Status: Sample rate, number of output channels, number of output samples per channel, and output channel configuration.
- Multi-channel: Fully re-entrant and multi-instancing capable.
The Dolby Pro Logic IIz decoder operates on PCM data received either through analog/digital input channels or from a decoder module. The Dolby Pro Logic IIz Decoder takes up to 7.1 input channels and outputs up to 9.1 audio channels. It contains a standard C-callable ‘push’ API with the added flexibility using ‘pull’ (or ‘poll’) by adding a light wrapper. The module has no dependencies on processor peripherals or registers, adding greater system flexibility and ease of use. The Dolby Pro Logic IIz Decoder on SHARC is provided with an API consistent with other audio decoder and post-processing modules produced by ADI.
In addition to the object libraries for Dolby Pro Logic IIx and Dolby Pro Logic IIz, the Dolby Pro Logic IIz release package includes source code for the Dolby Pro Logic IIz-specific post-processing functions additional to Dolby Pro Logic IIx. This gives customers the option of further optimizing the code for tighter integration with their system.
Each module supports the Analog Devices, Inc. (ADI) Blackfin or SHARC Processor family and is a licensed product that is available in object code format. Recipients must sign or accept a license agreement with ADI prior to being shipped or downloading the modules identified in the license agreement.
|SHARC Processor||Code RAM (KiB)||Data RAM (KiB)||Constant Data Tables (KiB)||MIPS|
- This table highlights example SHARC processors and expected MIPS performance.
- In the table above, all memory figures refer to one instance of DPLIIz Decoder and ro inclusive of the memory contribution from the DPLIIx library.
- “Data RAM” for one DPLIIz instance, includes Stack, Scratch, Instance/Stage, eight single-buffered input buffers and ten single-buffered output buffers, each containing 256 samples.
- The number of input samples to be processed per channel is configurable and affects the overall memory requirement of the DPLIIz module.
- MIPS figures indicated in the table have been measured using a sampling rate of 48 kHz, a block size of 256 samples, and are inclusive of the MIPS contribution from the DPLIIx library.
- VISA short-word mode is enabled when compiling ADSP-214xx library file, therefore the code size of ADSP-214xx library is smaller than that of ADSP-2136x library.
- 1 KiB = 1024 Bytes.
- Windows XP Professional SP3 (32-bit only).
- Windows Vista Business/Enterprise/Ultimate SP2 (32-bit only). It is recommended to install the software in a non-UAC-protected location.
- Windows 7 Professional/Enterprise/Ultimate (32 and 64-bit). It is recommended to install the software in a non-UAC-protected location.
- Minimum of 2 GHz single core processor, 3.3 GHz dual core is recommended.
- Minimum of 1 GB memory (RAM), 4 GB is recommended.
- Minimum of 2 GB hard disk (HDD) space is required.
- CrossCore® Embedded Studio for Analog Devices Processors.