DTS Symmetry Decoder, SHARC
The Digital Theatre Systems (DTS) Symmetry Decoder library for the SHARC processor dynamically adjusts the audio gain to maintain the same level of perceived loudness for a stereo source without causing audible distortion.
Each module supports the Analog Devices, Inc. (ADI) Blackfin or SHARC Processor family and is a licensed product that is available in object code format. Recipients must sign or accept a license agreement with ADI prior to being shipped or downloading the modules identified in the license agreement.
| SHARC Processor Family
|| Code memory (KiB)
|| Data RAM (KiB)
|| Constant Data Tables (KiB)
- MIPS measured using Fs = 48kHz, stereo input and output, optimal memory layout, running on a ADSP-21469.
- Code compatible across all ADSP-214xx processors, with silicon anomaly workarounds implemented.
- "Data RAM" for one instance, includes Stack, Scratch, Instance/State, Minimum Input and Output Single Buffers.
- Both input and output buffer size used for data memory calculation is 256 bytes (utilizing a frame size of 32 samples per channel).
- Frame size used for MIPS measurement is 256 samples per channel.
- Windows XP Professional SP3 (32-bit only).
- Windows Vista Business/Enterprise/Ultimate SP2 (32-bit only). It is recommended to install the software in a non-UAC-protected location.
- Windows 7 Professional/Enterprise/Ultimate (32 and 64-bit).
- Minimum of 2 GHz single core processor, 3.3 GHz dual core is recommended.
- Minimum of 1 GB memory (RAM), 4 GB is recommended.
- Minimum of 2 GB hard disk (HDD) space is required.
- CrossCore® Embedded Studio for Analog Devices Processors
- VisualDSP++ 5.0 for Analog Devices Processors and its latest update.
- SigmaStudio Graphical Development Tools version 3.7 Build 7 or later.
- SigmaStudio for SHARC Rel 2.0.0 or later.