G.729AB Codec, Blackfin
The G.729AB Voice Coder/Decoder library for the Blackfin processor implements a voice compression algorithm based on Conjugate-Structure Algebraic-Code-Excited Linear Prediction (CS-ACELP), which is compliant with ITU-T Recommendation G.729.
- API: C callable 'push'-type API
- Compatible with Analog Devices Blackfin processor family
- Rigorously tested
- The module has no dependencies on processor peripherals or registers, adding greater system flexibility and ease of use
- Conformance Standard: ITU-T G.729A Annex B
- Target Processor: Code compatible across the Blackfin processor family ADSP-BF5xx
- Framework dependencies: None. No dependencies on processor peripherals or registers
- Release format: Object code module with C source wrapper
- Input format: Mono channel, non-interleaved buffer
Encoder: signed 16-bits little-endian PCM samples
Decoder: 16 bit per bit of unpacked bit stream or, 1 bit per bit of packed bit stream
- Output format: Mono channel, non-interleaved buffer
Decoder: Signed 16-bits little-endian PCM samples.
Encoder: 16 bit per bit of unpacked bit stream or, 1 bit per bit of packed bit stream
- Input and output buffer samples per frame:
160 bytes for PCM buffers
164 bytes for unpacked bit stream buffers or, 14 bytes for packed bit stream buffers
- Sample Rate: 8 kHz
- Bit rate: 8 kbit/s
- Multi-channel: Fully re-entrant and multi-instancing capable
ITU-T Recommendation G.729 describes a voice compression algorithm based on Conjugate-Structure Algebraic-Code-Excited Linear Prediction (CS-ACELP). Annex A describes a reduced complexity version which is bit-stream interoperable with the full version of G.729. Annex B describes a silence compression scheme that includes Voice Activity Detection (VAD), Discontinuous Transmission (DTX) and Comfort Noise Generator (CNG) algorithms. G.729 is widely used as one of the key software components for packet based voice devices such as VoIP phones and private branch exchanges.
Each module supports the Analog Devices, Inc. (ADI) Blackfin or SHARC Processor family and is a licensed product that is available in object code format. Recipients must sign or accept a license agreement with ADI prior to being shipped or downloading the modules identified in the license agreement.
|Code memory (KiB)
||Data RAM (KiB)
|| Constant Data Tables (KiB)
|| Constant Data Tables (KiB)
- This table highlights example Blackfin processors and expected MIPS performance.
- MIPS measured using typical bit rates 8 kbit/s, Fs = 8 kHz, optimal memory layout with code and data in L1 memory, worst case test vector, mono channel.
- Both instruction and Bank A data cache have been enabled and data cache was set to write-back mode.
- "Data RAM" refers to a single instance and includes stack, scratch and instance/state memory as well as minimum-size input and output single buffers.
- 1 KiB = 1024 Bytes.
- Windows XP Professional SP3 (32-bit only).
- Windows Vista Business/Enterprise/Ultimate SP2 (32-bit only). It is recommended to install the software in a non-UAC-protected location.
- Windows 7 Professional/Enterprise/Ultimate (32 and 64-bit). It is recommended to install the software in a non-UAC-protected location.
- Minimum of 2 GHz single core processor, 3.3 GHz dual core is recommended.
- Minimum of 1 GB memory (RAM), 4 GB is recommended.
- Minimum of 2 GB hard disk (HDD) space is required.