MPEG-4 SP/ASP Encoder, Blackfin

MPEG4 SP/ASP Encoder
Manufactured by:

Features

  • Profiles: Simple Profile and Advanced Simple Profile.
  • Level: Up to L3 inclusive for SP, Up to L5 inclusive for ASP.
  • Frame types supported: I & P.
  • Input Resolution: Up to 5 Mega Pixel, D1 inclusive.
  • Entropy Encoder: VLC.
  • Number of Reference Frames: 1.
  • Pre-Processing: A simple 2:1 and 4:1 downscaling and de-interlacing for YUV420 and YUV422 formats. Pre-processing API to enable applications to plug-in own pre-processing blocks into encoder.
  • Scene Change Detection: Supported.
  • Scalability: Scalable Search Engine for MIPS and Quality trade-off.
  • Cache: Different configurations; No Cache, I-Cache and D-Cache.
  • Macroblock level quantization: Enabled for better rate control.
  • Bitrate control: VBR and CBR. Flexibility of switching between VBR and CBR during encoding.
  • Both NTSC & PAL format supported.
  • Max Output Resolution:
    • ADSP-BF561: Up to D1 at 30fps; 5MPixel at lower fps
    • ADSP-BF533: up to 1/2 D1 at 30fps; D1 at 15fps; 5Mpixel at lower fp
  • Conformance Standard: INTERNATIONAL STANDARD ISO/IEC14496-2:2004, Second edition 2004-06-01.
  • Target Processor: ADSP-BF533, ADSP-BF561, code compatible across the Blackfin processor family ADSP-BF5xx.
  • Release format: Object code module with C source wrapper.
  • Input format: ITU-R BT.656 format or YUV420 planar format or YUV422 progressive format from CMOS sensors.
  • Output format: Byte stream of elementary MPEG4.
  • Frame Rate: 2-30 frames per second.
  • Bit Rates: All bit rates specified by standard (VBR and CBR mode configurable for desired bit rates).
  • ROI : Region of Interest Encoding Support for YUV420 and YUV422 input formats.
  • ADSP-BF561 core loading: Symmetrical or Asymmetrical loading across core-A and core-B.
  • Multiple instance: Support simultaneous multiple channel encoding and update.
  • Target Processor: ADSP-BF527, ADSP-BF533, ADSP-BF561, ADSP-BF609 code compatible across the Blackfin processor family ADSP-BF5xx.

Product Details

This implementation of the MPEG-4 Encoder has been highly optimized to run on the Analog Devices ADSP-BF5xx Blackfin processor. It is a self-contained software module that is fully compliant with ISO/IEC14496-2, , Information technology — Coding of audio-visual objects — Part 2: Visual, Third edition 2004-06-01, specification.


The code has been implemented using Instruction and Data cache. To optimize video encoding performance, internal SRAMs for Program and Data memory and Memory DMA are also utilized effectively.

Licensing

X +

Each module supports the Analog Devices, Inc. (ADI) Blackfin or SHARC Processor family and is a licensed product that is available in object code format. Recipients must sign or accept a license agreement with ADI prior to being shipped or downloading the modules identified in the license agreement.


Performance Metrics

X +
MIPS/Memory Summary Table
Simple Profile:
Code Memory (KB) Data RAM (KB) Frame Buffer (MB)
Output Buffer (MB) Input Buffer (MB) MIPs Test Case Description
          SP Average SP Moving
Average Peak
 
75.89 37.32 1.41 1.00 1.08 234 240 CIF, 1.0 Mbps, 30 fps
75.89 37.32 1.41 1.00 1.08 410 421 ½ D1, 2.0 Mbps, 30 fps
75.89 37.32 1.41 1.00 1.08 850 891 D1, 4.0 Mbps, 30 fps

Advanced Simple Profile:
Code Memory (KB) Data RAM (KB) Frame Buffer (MB) Output Buffer (MB) Input Buffer (MB) MIPs Test Case Description
          SP Average SP Moving Average Peak  
75.89 37.32 1.41 1.00 1.08 283 292 CIF, 1.0 Mbps, 30 fps
75.89 37.32 1.41 1.00 1.08 501 512 ½ D1, 2.0 Mbps, 30 fps
75.89 37.32 1.41 1.00 1.08 1005 1047 CIF, 4.0 Mbps, 30 fps

  • MIPS measured using different bit rates and resolution - bit rates of 384Kbps, 30 fps, 176x144 (QCIF) size sequence, 1.0Mbps, 30 fps, 352x288 (CIF) size sequence and 4.0Mbps, 30 fps, 640x480 (VGA) size sequence, ITU-R BT.656 output, NTSC format, optimal memory layout on ADSP-BF561 rev 0.5 processor, for Simple and Advanced Simple Profile.
  • Measurements done with CAS1=3 for SDRAM, CCLK2=600, SCLK3=120 for ADSP-BF561.
  • Data cache and instruction cache are enabled. The cache is set in "write back" and "small cache" (DCBS=0) mode.
  • Memory DMA is used with 32 bit DMA.
  • "Data RAM" for one instance includes Stack, Scratch, Encoder Instance Memory, for D1 PAL resolution.
  • Frame Buffer for one instance of encoder and D1 PAL resolution.
  • Minimum Input and Output Single Buffers, for ITU-R BT656 D1 PAL input.
  • 1 MB = 1024 KB; 1 KB = 1024 Bytes.
  • MIPS number is quite similar for ADSP-BF609 processor.
  • NOTE: In deriving the "Moving Avg Peak" value, an 8 consecutive frame sliding window was used. An average cycle count was measured for each window of frames, and the worst case average cycle from all the sliding window measurements was determined to be the "Moving Avg Peak" value.


1CAS – Column Address Strobe Latency. Please refer BF5xx Hardware Reference Manual for more details on CAS.
2CCLK – Core clock
3SCLK – System Clock

Systems Requirements

X+
  • Windows XP Professional SP3 (32-bit only).
  • Windows Vista Business/Enterprise/Ultimate SP2 (32-bit only). It is recommended to install the software in a non-UAC-protected location.
  • Windows 7 Professional/Enterprise/Ultimate (32 and 64-bit). It is recommended to install the software in a non-UAC-protected location.
  • Minimum of 2 GHz single core processor, 3.3 GHz dual core is recommended.
  • Minimum of 1 GB memory (RAM), 4 GB is recommended.
  • Minimum of 2 GB hard disk (HDD) space is required.
  • CrossCore Embedded Studio for Analog Devices Processors.
  • VisualDSP++ for Analog Devices Processors.

Related Hardware

X+

EZ-Kits

See All 4 EZ-Kits

Extender Boards