JPEG Decoder, Blackfin
The JPEG (Joint Photographic Experts Group) Decoder library for the Blackfin processor is fully compliant with ISO/IEC 10918-1:1993 (ITU-T T.81) and can be used to build a Motion-JPEG video system, for example using the AVI file format.
- Target Processor: Code compatible across the Blackfin ADSP-BF5xx and ADSP-BF6xx processor Family
- Release format: Object code module with C source wrapper
- Input format: JPEG bit streams encoded using Baseline, Extended Sequential DCT Process (Huffman coding), or Progressive DCT Process (Huffman coding)
- Supported Transport Formats: A separate sub-module is required to demux JPEG frames from a transport stream. Example source code is available for M-JPEG AVI
- Supported Meta-data File Formats: A separate sub-module is required to parse meta-data from a JPEG bit stream. Example source code is available for EXIF, JFIF, and Adobe®
- Output format: RGB, YUV 4:4:4, YUV 4:2:2, rotated YUV 4:2:2, YUV 4:2:0, or Y-only (YUV 4:0:0 / monochrome)
- Output data resolution: 8 bits
- Framework dependencies: None
- Multi-threading: Fully re-entrant and multi-instancing capable
- Compliant with ISO/IEC 10918-1:1993 (ITU-T T.81)
- Rigorous interoperability testing across many commercially available platforms and open source viewers/applications
The JPEG decoder has been highly optimized to run on the Analog Devices' Blackfin® processor family. It is a self-contained software module that is fully compliant with ISO/IEC 10918-1:1993 (ITU-T T.81). This software has undergone rigorous interoperability testing across many commercially available platforms, and open source applications. This module can be used to build a Motion-JPEG video system, for example using the AVI file format.
The module uses a C-callable API that includes a number of system interface hooks via user call-back functions. This allows better customization and optimization of data input/output integration, and meta-data processing (for example EXIF). The code has no dependencies on processor peripherals or registers, adding greater system flexibility and ease of use.
| Average Cycles
|Constant Data Tables
- This table highlights example Blackfin processors and average cycle counts. The ADSP-BF609 processor includes additional L2 on-chip memory which can help reduce cycles when fully utilized. Similarly, processors with higher bandwidth external memory interfaces (32-bit versus 16-bit, and DDR versus SDRAM) will also help reduce overall cycle requirements.
- Cycles measured using a compressed Mandrill 512x512 YUV420 image encoded in sequential mode, compression rate 1.8 bits per pixel (compression ratio 14.2), running on BF533/BF609 with optimum memory layout.
- BF533 Core Clock = 594 MHz, System Clock = 118 MHz; BF609 Core Clock = 500 MHz, System Clock = 250 MHz, Dynamic Mem Clock = 250 MHz.
- Code compatible across all Blackfin processors, with silicon anomaly workarounds implemented.
- "Data RAM" for one instance, includes scratch buffer and stack, and minimum heap memory.
- 1 KiB = 1024 Bytes.
- Windows XP Professional SP3 (32-bit only)
- Windows Vista Business/Enterprise/Ultimate SP2 (32-bit only). It is recommended to install the software in a non-UAC-protected location.
- Windows 7 Professional/Enterprise/Ultimate (32 and 64-bit). It is recommended to install the software in a non-UAC-protected location.
- Windows 8 Professional/Enterprise (32 and 64-bit). It is recommended to install the software in a non-UAC-protected location.
- Minimum of 2 GHz single core processor, 3.3 GHz dual core is recommended.
- Minimum of 1 GB memory (RAM), 4 GB is recommended.
- Minimum of 2 GB hard disk (HDD) space is required.
- CrossCore Embedded Studio for Analog Devices Processors.
- VisualDSP++ 5.1 for Analog Devices with the latest update.