The Fundamentals of LDO Design and Applications
Frequently Asked Questions About LDOs
Depending on your particular design your selection criteria may differ. However, as a general rule you should use the list below in the order that they appear.
- Input voltage range
- Output voltage, fixed or adjustable
- Output accuracy over line, load, and temperature
- Load current requirement
- Dropout voltage
- Power supply rejection ratio (PSRR)
- Output noise
- Quiescent current and shutdown current
An LDO’s design is usually optimized for a specific value of load bypass capacitor. Increasing the load capacitance above the recommended value can improve load transient response. However, when a larger output capacitor is chosen, the input bypass capacitor should be increased to match it. Note: the input and output capacitors should be placed as close as possible to the LDO.
Any good quality ceramic capacitors can be used, as long as they meet the minimum capacitance and maximum effective series resistance (ESR) specifications listed on the LDO data sheet. Ceramic capacitors using X5R or X7R dielectrics are highly recommended as these have good temperature stability and a low voltage coefficient.
Designs using a bipolar transistor for the pass element exhibit a large increase in ground current as output load increases, reaching ~5% of load current. MOSFET based LDOs are more energy efficient as the ground current increase with load is minimal. The ground current for MOSFET based LDOs is typically below 0.1% of full load.
Power supply rejection ratio specifies the ability of an LDO to prevent output voltage fluctuations when there are variations in input voltage. PSRR is usually specified at a specific frequency, for example 60 dB rejection at 120 Hz. Battery-based systems should employ LDOs that maintain high PSRR at low battery voltages, i.e. with a low input-output voltage differential.
LDOs will reject input noise up to tens, even hundreds of kHz. High frequency (1 MHz and up) switching noise rejection is primarily a function of the output bypass capacitor network; the LDO’s loop bandwidth is too low above 1 MHz to provide any noise reduction. The LDO forms an impedance divider with the pass element and the output capacitor network and load; this provides noise rejection at high frequency.
An LDO’s internal voltage reference is the primary source for output noise. It is usually specified in microvolts rms over a specific bandwidth, such as 25 ìV rms from 1 kHz to 100 kHz. This low level noise is much lower than the switching transients and harmonics from a switch mode dc-to-dc converter. Some LDOs feature a bypass pin to filter reference voltage noise with a capacitor to ground. Following the data sheet specified input, output, and bypass capacitors usually results in a unproblematic noise level.
None of Analog Devices LDOs need a minimum load current. However, there are many competitive LDOs on the market that do require a minimum load, some needing as much as several mA.
- An enable input to control LDO turn-on and turn-off for system power savings
- Programmable soft-start to limit inrush current, control output voltage rise-time during startup, and enable voltage sequencing
- Tracking feature, which allows the LDO output to follow an external voltage rail or reference
- A bypass pin that allows an external capacitor to reduce output voltage noise and improve power supply rejection
- A power-good output that indicates when the output is in regulation
- Thermal shutdown that turns the LDO off if its temperature exceeds the specified level
- Current limit function to control the LDO’s output current and power dissipation