ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design. ADIsimCLK version 1.6 expands on previous versions with an added model of the AD9528 low jitter clock generator.
ADIsimCLK is a highly successful tool for predicting phase noise and jitter for ADI clock products. Features include:
- jitter performance - broadband and SONET specifications
- phase noise performance
- phase noise impact - ACI/ACR, EVM, phase jitter etc.
- jitter impact on ADC performance - SNR, ENOB
- accurate timing analysis (logic analyzer display)
ADIsimCLK models PLL frequency synthesizers + external VCOs, as well as integrated PLL/VCOs. Analysis includes:
- phase noise analysis including reference, VCO, loop filter and phase detector contributions
- non-linear transient analysis - for accurate determination of lock time
ADIsimCLK Version 1.6 (released April 2015) Once the zip file has been stored locally, it can be extracted and run by clicking on "setup.exe". Please note: Any old versions should be uninstalled before installing the latest version.
ADIsimCLK is extremely user friendly and easy to use. The ADIsimCLK wizard enables the designer to observe detailed performance data for a 'simulated' clock distribution design within minutes. Optimization of the clock circuit can be accomplished in this interactive environment with spreadsheet-like simplicity and interactivity. Contrary to the traditional methods where to design, build and then measure parameters takes days, ADIsimCLK enables the user to change the circuit design and observe immediate performance changes.
In summary, ADIsimCLK allows the designer to work at a higher level and directly modify parameters such as the loop bandwidth, divide ratios, phase offsets, output frequencies, and the effects of the changes on performance are shown instantly (and without burning fingers with a soldering iron!). With traditional design techniques, the evaluation of new devices requires construction, measurement and hand optimization of a prototype, which is a significant barrier to change and is often a key reason for the continual use of 'old' clock distribution chips.