This toolis both a demonstration and design tool for the AD5933 and AD5934 Impedance Converter / Network Analyzer parts. In the default (startup) mode it demonstrates the steps needed to configure and use the part. A design mode is also available which permits free control of the user interface and the calculation of values for programming the internal registers. The active mode is selected by means of a pulldown ("DEMO") in the upper left corner of the gray data entry area at the bottom of the applet.
In demonstration mode, six buttons are sequentially enabled to illustrate stages in programming the AD5933/4 device. At each stage, the relevant registers are highlighted and enabled, and help is given in the help box at bottom right. After the appropriate configuration for a step has been completed, click on the enabled button to proceed to the next step.
To take full control of the tool at any time, select "Design mode" from the pulldown menu. All fields are then enabled, and the demonstration mode buttons replaced with register fields. Data entered in the intuitive fields such as "Start", "Increment", etc. are transcribed into the corresponding individual register fields in the register area at bottom left. Enter must be pressed after values are modified for the tool to accept and process the new data. Modified but unprocessed values are indicated by a black box around the changed quantity.
There are three displays available, sequentially selected by means of the "Switch Display" button at center-right. The first display is of a block diagram. As you click in the pseudo-register fields the corresponding block in the block diagram should highlight. If you click "Switch Display" once, an Impedance vs. Frequency chart is displayed, showing the theoretical impedance in blue and the "measured" (simulated) impedance in red. (Note the deviations that occur below 1KHz due to a 1ms DFT window and above 100KHz due to limitations on internal bandwidth.) Clicking "Switch Display" brings up a output-input scaling plot that is useful for understanding the voltage relationships and how they are affected by Z(ω), RFB, Output Level and ADC Gain settings. In particular, this display is most useful for selecting Output level, Rfb and ADC Gain so as to not saturate the ADC. Clicking "Switch Display" once more returns the display to the Block Diagram.
Conceptually, the AD5933/4 consist of a DDS output block coupled by means of an external impedance, Z(ω), to an ADC feeding a DFT. More than one sample can automatically be collected, so initialization consists of programming a span to be measured using the start, increment and increment count pseudo-registers and then choosing a combination of RFB, output level and input gain such that the maximum non-saturated admittances are obtained.
The convert these raw admittance samples into accurate impedance measurements, they must be calibrated against the measured value(s) of a known impedance, to derive a gain factor for the individual part at temperature. The gain factor is defined as admittance/code, and used as follows:
In the simplest case, calibration consists of measuring a precision resistor at the center point of the frequency span of interest, however, for greater accuracy it may be desirable to sample both ends of the span and use a linear interpolation between the end points to compute a gain factor that is a function of frequency.
||1 / ZKNOWN
CodeUNKNOWN * Gain Factor
Another factor affecting accuracy is the finite precision of the DDS and A/D converters. To that end, it's important to choose the combination of RFB, Output level and ADC Gain that maximizes the ADC Input waveform (Output-Input Scaling Chart), without saturating the A/D input at any point over the measured frequency span. The Output-Input chart only simulates the waveform for the base (Start) frequency, however, saturation is also detectable using the Impedance vs. Frequency chart where it can be seen in the deviation of the "Measured" impedacne from the Ideal. The deviation in that chart below fS/1024 is due to the 1024-pt sample limit. The deviation above 100KHz is due to the internal low-pass filter. Deviations beteen 250 or 1KHz and 100KHz are likely due to saturating the A/D converter.
THIS TOOL IS INTENDED AS A DEMO RATHER THAN AS AN EVALUATION TOOL AND AS SUCH NO GUARANTEE IS GIVEN TO REFLECT ACTUAL PERFORMANCE OVER ALL CONDITIONS. IT IS RECOMMENDED THAT AN EVALUATION BOARD BE OBTAINED TO EVALUATE PERFORMANCE UNDER SPECIFIC CONDITIONS. Please note that low-frequency performance in particular (below ~ 5kHz for the AD5933 with 16MHz MCLK, lower frequencies measurable by proportionate reduction of MCLK) may differ substantially from the actual part. Also, typical values for output impedance are used in calculations; variation in real-world output impedance may limit the accuracy of low impedance measurements.
Linux users will probably find that V1.5.X of the Sun Java runtime fixes major problems with pulldown menus, however, even using an older plugin it is generally possible to manipulate the problem pulldowns by first selecting them and then using the up-down arrow keys.
Note: For certain extreme configurations, the admittance calculation can yield zero, in which case the impedance magnitude is infinite. To keep the display readable, the maximum displayed impedance is limited to 100MΩ.
The impedance samples available in the real and imaginary data registers are for demonstration purposes only.
The latest version of the Java Applet Plugin is required to run this design tool. It can be downloaded here.
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