Application Notes (1)
Design Handbooks (2)
- DAC, DDS, PLL's, and Clock Distribution (pdf, 7676 kB)
- Optimizing Data Converter Interfaces (pdf, 1677 kB)
Tutorials (2)
- MT-008: Converting Oscillator Phase Noise to Time Jitter (pdf, 123 kB)
- MT-200: Minimizing Jitter in ADC Clock Interfaces (pdf, 447 kB)
Webcasts (2)
-
Fundamentals of Designing with Analog to Digital Converters
BACK BY POPULAR DEMAND: an update to The Fundamentals of the Analog to Digital Converter (ADC) webcast, including basic ADC architectures, understanding ADC errors, how to read an ADC data sheet, and how to choose the right ADC. Includes the latest on ADC products and technology. -
Performance Clocks: Demystifying Jitter
Join us as we delve into the realm of sub-picosecond jitter clocks. The relationship between jitter and phase noise will be explored in detail and methods for measuring sub-picosecond jitter and ultra low phase noise will be presented and discussed.
Analog Dialogue (2)
-
Analog-to-Digital Converter Clock Optimization: A Test Engineering Perspective
(Analog Dialogue, Vol. 42, February 2008) -
Termination of High-Speed Converter Clock Distribution Devices
(The Back Burner, January 2010)
