Clock and Timing

High-performance Clock ICs and Timing IC solutions have the critical responsibility of synchronizing data packet transfer, and generating and distributing the clock tree that controls the system blocks in wired and wireless networks. Analog Devices has a portfolio of products that deliver low-jitter performance coupled with integrated features that enhances overall system performance.

Analog Devices’ Clock ICs and Timing Solutions enable new architectures, lower development and manufacturing costs, and shorten your design time. Products feature low jitter and phase noise for clock cleanup, synchronization, generation, delay, and distribution. Clocking high-speed A/D converter and D/A converter stages is an important function in wireless networks. ADI is the world leader in data converters, and our clocking solutions are co-developed under the same roof as our high-speed converters; this optimal design and testing environment insures the best clock performance, as no one knows more about clocking data converters than ADI.

Likewise, ADI’s clock expertise has translated into a portfolio of wired network clocks that deliver the same high-level of jitter performance along with industry-leading innovation in all-digital PLLs and holdover/switchover circuitry specific to wired applications. In addition to its clock expertise ADI also provides clock IC and timing solution related technical documents, tutorials, design and simulation tools and support. Design Engineers can learn about the functions of clock generation and distribution and the important performance specifications in the DAC, DDS, PLL’s, and Clock Distribution Design Handbook, (pdf. 7.50 MB). They can utilize the ADIsimCLK™ Design and Evaluation Software for predicting phase noise and jitter for ADI clock IC products.

Clock and Timing

Clock and Timing ICs for Wireline Applications

EZone

EngineerZone Support Community: Latest Clock and Timing Discussions

Documentation And Resources

Title Content Type File Type
AN-0982: The Residual Phase Noise Measurement  (pdf, 710 kB) Application Notes PDF
AN-0983: Introduction to Zero-Delay Clock Timing Techniques  (pdf, 162 kB) Application Notes PDF
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter  (pdf, 291 kB) Application Notes PDF
AN-501: Aperture Uncertainty and ADC System Performance  (pdf, 227 kB)
A Key Concern in IF Sampling is that of Aperture Uncertainty (Jitter)
Application Notes PDF
Use Circuits from the Lab™ in Your Next Design
Watch how two engineers were able to use Analog Devices Circuits from the Lab to help solve their design challenge. From test data to HW evaluation, to project integration, we make it easy to save time while lowering the risk in your circuit design.
Videos HTML
How to Read a Datasheet
What is in a datasheet, and how can the information it contains help you select the right part for your design? This wide-ranging and informative webcast will take you through a typical datasheet and explain the full meaning behind many often misunderstood specs.
Webcasts WEBCAST
Network Clock: How To Achieve Maximum System Up Time
In this in-depth Webcast, our clock expert will explore the technical implications of this very real system scenario, and discuss the incorporation of seamless reference switchover and holdover technology that maintains a stable, low-jitter, system clock during periods of switchover, and complete reference loss, conditions.
Webcasts WEBCAST
UG-311: Reliability Handbook  (pdf, 3248 kB) User Guides PDF
Multi-output, 1.65-GHz Clock Buffer and Divider Delivers Low Jitter to Optimize Noise Performance in Ultra-high-speed Data Converters (13 Feb 2013) Press Releases HTML
Dual Adaptive Clock Translator Supports Wide Range of Wired Network Applications including OTN De-mapping and High-density Line Cards (27 Jul 2012) Press Releases HTML
Analog Devices’ Webcast Addresses The Fundamentals Of Clock Synthesis And Distribution (17 Jan 2012) Press Releases HTML
Can I exceed the parameters specified in the absolute maximum ratings table? FAQs/RAQs HTML
What is latch-up and how can I prevent it? FAQs/RAQs HTML
ADIsimCLK Design and Evaluation Software
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
ADIsim Design/Simulation Tools HTML
ADIsimDDS™
The purpose of this tool is to assist a user in selecting and evaluating Analog Devices, Direct Digital Synthesis (DDS) IC's. It allows a user to select a device, enter the desired operating conditions and evaluate it's general performance.
ADIsim Design/Simulation Tools HTML
AD9523/AD9523-1 IBIS Model IBIS Models HTML
AD9522-x IBIS Models IBIS Models HTML
AD9520-x IBIS Models IBIS Models HTML
ADCLK950 Evaluation Tools Documentation HTML
AD9551 Evaluation Tools Documentation HTML
ADCLK946 Evaluation Tools Documentation HTML
ADCLK854 Evaluation Tools Documentation HTML
ADCLK846 Evaluation Tools Documentation HTML
ADCLK914 Evaluation Tools Documentation HTML
ADCLK9xx Evaluation Boards/Tools Documentation HTML
Glossary of EE Terms Glossary HTML
ADIsimCLK Design and Evaluation Software
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
Software and Tools HTML
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