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Clock and Timing

High-performance Clock ICs and Timing IC solutions have the critical responsibility of synchronizing data packet transfer, and generating and distributing the clock tree that controls the system blocks in wired and wireless networks. Analog Devices has a portfolio of products that deliver low-jitter performance coupled with integrated features that enhances overall system performance.

Analog Devices’ Clock ICs and Timing Solutions enable new architectures, lower development and manufacturing costs, and shorten your design time. Products feature low jitter and phase noise for clock cleanup, synchronization, generation, delay, and distribution. Clocking high-speed A/D converter and D/A converter stages is an important function in wireless networks. ADI is the world leader in data converters, and our clocking solutions are co-developed under the same roof as our high-speed converters; this optimal design and testing environment insures the best clock performance, as no one knows more about clocking data converters than ADI.

Likewise, ADI’s clock expertise has translated into a portfolio of wired network clocks that deliver the same high-level of jitter performance along with industry-leading innovation in all-digital PLLs and holdover/switchover circuitry specific to wired applications. In addition to its clock expertise ADI also provides clock IC and timing solution related technical documents, tutorials, design and simulation tools and support. Design Engineers can learn about the functions of clock generation and distribution and the important performance specifications in the DAC, DDS, PLL’s, and Clock Distribution Design Handbook, (pdf. 7.50 MB). They can utilize the ADIsimCLK™ Design and Evaluation Software for predicting phase noise and jitter for ADI clock IC products.

Have questions? Visit the Clock ICs and Timing Support Community on EngineerZone.

EngineerZone: Latest Clock and Timing Discussions

NEW PRODUCTS

  • ADF4151- Fractional-N/Integer-N PLL Synthesizer
    ADF4151:Fractional-N/Integer-N PLL Synthesizer

    The ADF4151 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers if used with an external voltage controlled oscillator (VCO), loop filter, and external reference frequency.

    The ADF4151 is used with external VCO parts and is footprint and software compatible with the ADF4350. The part consists of a low MoreRead more

    Data Sheet Rev B, 12/2011 (pdf 473kB)
    ADF4151 Diagram
  • ADF4196- Low Phase Noise, Fast Settling 6 GHz PLL Frequency Synthesizer
    ADF4196:Low Phase Noise, Fast Settling 6 GHz PLL Frequency Synthesizer

    The ADF4196 frequency synthesizer can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations, and the fast settling feature makes the ADF4196 suitable for pulse Doppler radar applications.

    The ADF4196 consists of MoreRead more

    Data Sheet Rev B, 12/2011 (pdf 2801kB)
    ADF4196 Diagram
  • AD9577- Clock Generator with Dual PLLs, Spread Spectrum, and Margining
    AD9577:Clock Generator with Dual PLLs, Spread Spectrum, and Margining

    The AD9577 provides a multioutput clock generator function along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. The PLLs have I2C programmable output frequencies and formats. The MoreRead more

    Data Sheet Rev 0, 10/2011 (pdf 476kB)
    AD9577 Diagram
  • AD9557- Dual-Input Multiservice Line Card Adaptive Clock Translator
    AD9557:Dual-Input Multiservice Line Card Adaptive Clock Translator

    The AD9557 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9557 generates an output clock synchronized to one or two external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled MoreRead more

    Data Sheet Rev 0, 10/2011 (pdf 1299kB)
    AD9557 Diagram
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