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About ADI
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NEWS
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14 Aug 2009
Analog Clocking ICs
Replace Expensive, High-Frequency VCOs; Improve Jitter. -
13 Aug 2009
New Webinar! Differential Circuit Design Techniques for Communication Applications
This webinar explores the advantages of differential design techniques for today's high performance communication systems. -
24 Feb 2009
Analog Devices Introduces
Simplified Clock Generator Architecture
NEW PRODUCTS
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ADF5001- 4 GHz to 18 GHz Divide-by-4 Prescaler
The ADF5001 prescaler is a low noise, low power, fixed RF divider block that can be used to divide down frequencies as high as 18 GHz to a lower frequency suitable for input into a PLL IC, such as the ADF4156 or ADF4106. The ADF5001 provides a divide-by-4 function. The ADF5001 operates off More
Data Sheet Rev 0, 11/2009 (pdf 268kB)
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AD9571- Ethernet Clock Generator, 10 Clock Outputs
The AD9571 provides a multioutput clock generator function comprising a dedicated PLL core that is optimized for Ethernet line card applications. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit More
Data Sheet Rev 0, 09/2009 (pdf 360kB)
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AD9572- Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs
The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequencysynthesizers to maximize network performance. Other applications with demanding phase noise and More
Data Sheet Rev 0, 08/2009 (pdf 415kB)
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ADCLK948- Two Selectable Inputs, 8 LVPECL Outputs SiGe Clock Fanout Buffer
The ADCLK948 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon german-ium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter.
The device has two selectable differential inputs via the IN_SEL control pin. Both inputs are equipped with center tapped, differential, 100 Ω on-chip termination More
Data Sheet Rev 0, 07/2009 (pdf 709kB)
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