NEW PRODUCTS
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ADF4151- Fractional-N/Integer-N PLL Synthesizer
The ADF4151 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers if used with an external voltage controlled oscillator (VCO), loop filter, and external reference frequency.
The ADF4151 is used with external VCO parts and is footprint and software compatible with the ADF4350. The part consists of a low More
Data Sheet Rev B, 12/2011 (pdf 473kB)
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ADF4196- Low Phase Noise, Fast Settling 6 GHz PLL Frequency Synthesizer
The ADF4196 frequency synthesizer can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations, and the fast settling feature makes the ADF4196 suitable for pulse Doppler radar applications.
The ADF4196 consists of More
Data Sheet Rev B, 12/2011 (pdf 2801kB)
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AD9577- Clock Generator with Dual PLLs, Spread Spectrum, and Margining
The AD9577 provides a multioutput clock generator function along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. The PLLs have I2C programmable output frequencies and formats. The More
Data Sheet Rev 0, 10/2011 (pdf 476kB)
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AD9557- Dual-Input Multiservice Line Card Adaptive Clock Translator
The AD9557 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9557 generates an output clock synchronized to one or two external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled More
Data Sheet Rev 0, 10/2011 (pdf 1299kB)
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