Expanding Family of Integrated Clock ICs
...providing clean clock generation and distribution with
sub-picosecond jitter performance
More Information is available:
Family Features
AD9513, AD9514, AD9515
- Pin-programmable divides, phase, delay; no serial port required
- Clock inputs/LVPECL outputs up to 1.6 GHz
- Supports LVPECL/LVDS/CMOS outputs
- Ultra-low jitter performance (additive jitter <300 femtoseconds rms)
- Excellent output isolation
- Small 32 LFCSP package
AD9510, AD9511, AD9512
- Low-phase-noise Clock Outputs with Sub-Picosecond Jitter optimized for clocking ADCs,
DACs, digital up/down converters, DDSs, MxFEs, ASICs
- Programmable Dividers, Phase Offsets, Delay Blocks
- Integrated PLL Frequency Synthesizer Core
Applications
Clock Distribution:
- Low jitter, low phase noise clock distribution
- Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFEs
- High performance wireless infrastructure transceivers
- High performance instrumentation
- Broadband infrastructure
- Automated test equipment
Clock Generation:
- Clocking high performance data converters
- Base station clocking applications
- Network (SONET/SDH) clocking
- Gigabit Ethernet (GbE) clocking
- Instrumentation clocking circuits
| AD9510 |
1200/800/250 |
4 LVPECL
4 LVDS/CMOS |
250 Additive |
1.6GHz PLL, 8-channel clock distribution |
| AD9511 |
1200/800/250 |
3 LVPECL
2LVDS/CMOS |
250 Additive |
1.6GHz PLL, 5-channel clock distribution |
| AD9512 |
1200/800/250 |
3 LVPECL
2LVDS/CMOS |
250 Additive |
5-channel clock distribution |
| AD9513 |
800/250 |
3 LVDS/CMOS |
300 Additive |
3-channel clock distribution |
| AD9514 |
1600/800/250 |
2 LVPECL
1 LVDS/CMOS |
225 Additive |
3-channel clock distribution |
| AD9515 |
1600/800/250 |
1 LVPECL
1 LVDS/CMOS |
225 Additive |
2-channel clock distribution |
| AD9540 |
655 |
1 CML, PECL-Compliant |
700 Total |
655 MHz Low Jitter Clock Generator |
