The AD9577 provides a multioutput clock generator function along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. The PLLs have I2C programmable output frequencies and formats. The fractional-N PLL can support spread spectrum clocking for reduced EMI radiated peak power. Both PLLs can support frequency margining.
The first integer-N PLL section (PLL1) consists of a phase frequency detector (PFD), a charge pump (CP), a low noise voltage controlled oscillator (VCO), a programmable feedback divider, and two independently programmable output dividers. By connecting an external crystal or reference clock to the REFCLK pin, frequencies up to 637.5 MHz can be synchronized to the input reference. Each output divider and feedback divider ratio can be factory or I2C programmed for the required output rates.
A second fractional-N PLL (PLL2) with a programmable modulus allows VCO frequencies that are fractional multiples of the reference frequency to be synthesized. Each output divider and feedback divider ratio can be factory programmed for the required output rates, up to 637.5 MHz. This fractional-N PLL can also operate in integer-N mode for the lowest jitter.
Up to four differential output clock signals can be configured as either LVPECL or LVDS signaling formats. Alternatively, each output pair can be configured for up to eight CMOS outputs. Combinations of these formats are supported. No external loop filter components are required, thus conserving valuable design time and board space. The AD9577 is available in a 40-lead, 6 mm × 6 mm LFCSP package and can operate from a single 3.3 V supply. The operating temperature range is −40°C to +85°C.
|Title||Content Type||File Type|
|AD9577: Clock Generator with Dual PLLs, Spread Spectrum, and Margining Data Sheet (Rev 0, 10/2011) (pdf, 476 kB)||Data Sheets|
|UG-551: XStream™ ADI-BERT: An 11.3 Gbps Bit Error Rate Tester Solution Based on ADN2915, a Continuous-Tuning Wideband Clock and Data Recovery IC (pdf, 1884 kB)||User Guides|
|RAQs index||Rarely Asked Questions||HTML|
|Glossary of EE Terms||Glossary||HTML|
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