AD9510:  1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and low phase noise in order to maximize data converter clocking ...More

Two evaluation boards are available for the AD9510:
AD9510/PCB: Evaluation Board without VCO or VCXO or loop filter
AD9510-VCO/PCB: Evaluation Board with 245.76MHz VCXO, loop filter

An Overview of the Clock Distribution/Generation Family is available.

AD9510:  1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

Product Description

The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and low phase noise in order to maximize data converter clocking performance. Four independent LVPECL and four LVDS clock outputs operate to 1.2 GHz and 800 MHz respectively. Optional CMOS clock outputs available to 250 MHz.

The PLL section consists of a programmable reference divider, R; a low-noise phase frequency detector, PFD; a precision charge pump, CP; and a programmable feedback divider, N. By connecting an external VCXO or VCO to the CLK2 and CLK2B pins, PLL output frequencies up to 1.6 GHz may be synchronized to the input reference, REFIN.

The clock distribution section provides LVPECL outputs and outputs that may be programmed to either LVDS or CMOS. Each output has a programmable divider, which may be bypassed or set to divide by any integer up to 32.

Each divider allows the user to change the phase of one clock output relative to another clock output. This phase select functions as a coarse timing adjustment. Some outputs also feature programmable delay elements with a user-selected, fullscale range to 10 ns. This fine tuning delay block is programmed with a 5-bit word, which gives the user 32 possible delays from which to choose.

The AD9510 is ideally suited for data converter clocking applications where maximum converter performance is achieved with sub-picosecond jitter encode signals.

The AD9510 is available in a 64-lead LFCSP and is specified from -40°C to +85°C. The part may be run from a single 3.3 V supply. Users wishing to extend the voltage range for external VCOs may run the charge pump supply, VCP, to 5.5V.

Applications

  • Low jitter, low phase noise clock distribution
  • Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFE™ Converters
  • Wireless infrastructure transceivers
  • High performance instrumentation
  • Broadband infrastructure

Features

  • Phase locked loop (PLL) Core
    Reference input frequencies to 250 MHz
    Programmable dual-modulus prescaler
    Programmable charge pump (CP) current
    Separate CP supply (VCP) extends tuning range
  • Two 1.6 GHz, differential clock inputs
  • 8 programmable dividers, 1 to 32, all integers
  • Phase select for output-to-output coarse delay adjust
  • Four independent 1.2 GHz LVPECL outputs
    Additive output jitter , 225 fs RMS
  • Four independent 800 MHz/250 MHz LVDS/CMOS outputs
    Additive output jitter, 275 fs RMS
    Fine delay adjust on 2 outputs, 5-bit delay words
  • Serial control port
  • Space-saving 64-lead LFCSP

Diagrams

AD9510 Diagram
Functional Block Diagram for AD9510

Specifications

Primary Clock Function Distribution
On-Chip Multiplier PLL Core
+Supply Voltage (V) 3.3V
Max Input Frequency 1.6GHz
# of Outputs 8
Max f-out (MHz) 1200MHz
I/O Interface Serial
Package 64-LFCSP
Output Logic CMOS,LVDS,LVPECL
Product Description Multi-Output Clock Generator

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Part# Product Description +Supply Voltage (V) # of Inputs # of Outputs On-Chip VCO or DCO Max f-out (MHz) Output Logic Random Jitter (ps-RMS) Package Price* (1000-4999)
AD9510 Multi-Output Clock Generator 3.3 1 8 No 1200 CMOS, LVDS, LVPECL 0.225 64-LFCSP $12.09
AD9511 Multi-Output Clock Generator 3.3 1 5 No 1200 CMOS, LVDS, LVPECL 0.225 48-LFCSP $10.07
AD9512 Clock Divider 3.3 1 5 No 1200 CMOS, LVDS, LVPECL 0.225 48-LFCSP $9.06
AD9513 Clock Divider 3.3 1 3 No 800 CMOS, LVDS 0.3 32-LFCSP $6.02
AD9514 Clock Divider 3.3 1 3 No 1600 CMOS, LVDS, LVPECL 0.225 32-LFCSP $6.02
AD9515 Clock Divider 3.3 1 2 No 1600 CMOS, LVDS, LVPECL 0.225 32-LFCSP $4.81
AD9516-0 Multi-Output Clock Generator 3.3 2 14 Yes 2950 CMOS, LVDS, LVPECL 0.4 64-LFCSP $12.65
AD9516-1 Multi-Output Clock Generator 3.3 2 14 Yes 2650 CMOS, LVDS, LVPECL 0.4 64-LFCSP $12.65
AD9516-2 Multi-Output Clock Generator 3.3 2 14 Yes 2335 CMOS, LVDS, LVPECL 0.4 64-LFCSP $12.65
AD9516-3 Multi-Output Clock Generator 3.3 2 14 Yes 2250 CMOS, LVDS, LVPECL 0.4 64-LFCSP $12.65
AD9516-4 Multi-Output Clock Generator 3.3 2 14 Yes 1800 CMOS, LVDS, LVPECL 0.4 64-LFCSP $12.65
AD9517-0 Multi-Output Clock Generator 3.3 2 12 Yes 2950 CMOS, LVDS, LVPECL 0.4 48-LFCSP $11.54
AD9517-1 Multi-Output Clock Generator 3.3 2 12 Yes 2650 CMOS, LVDS, LVPECL 0.4 48-LFCSP $11.54
AD9517-2 Multi-Output Clock Generator 3.3 2 12 Yes 2335