CN0259: High Performance 65 MHz Bandwidth Quad IF Receiver with Antialiasing Filter and 184.32 MSPS Sampling Rate

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OVERVIEW

Circuit Note PDF, 06/2012 (pdf, 201 kB)
Benefits & Features
  • Quad IF Receiver
  • 65MHz Bandwidth
  • 184.32MSPS Sampling Rate
  • 70.1dB SNR @ 140MHz Input
  • 70dB SFDR @ 140MHz Input
Products Used
    Applications: 
  • Communications
  • Radar
  • Communications
Design Resources
Design & Integration Files
  • Schematic
  • Bill of Materials
  • Gerber Files
  • Assembly Drawing
Download Design Files (747 kB)
Evaluation Hardware
Part numbers with "Z" indicate RoHS Compliance.
Boards checked are needed to evaluate this circuit.
  • EVAL-CN0259-HSCZ ($385.00) High Performance 65 MHz Bandwidth Quad IF Receiver with Antialiasing Filter and 184.32 MSPS Sampling Rate
  • HSC-ADC-EVALCZ ($607.20) High Speed Eval Control Board
Check Inventory & Purchase

CIRCUIT FUNCTION AND BENEFITS

The circuit, shown in Figure 1, is a 65 MHz bandwidth receiver front end based on the ADL5565 ultrahigh dynamic range differential amplifier driver and the 11-bit, 200 MSPS AD6657A quad IF receiver.

The fourth-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and IF receiver. The total insertion loss due the filter network and other resistive components is only 2.0 dB. The overall circuit has a bandwidth of 65 MHz, with the low-pass filter having a 1 dB bandwidth of 190 MHz and a 3 dB bandwidth of 210 MHz. The pass-band flatness is 1dB.

The circuit is optimized to process a 65 MHz bandwidth IF signal centered at 140 MHz with a sampling rate of 184.32 MSPS. The SNR and SFDR measured with a 140 MHz analog input across the 65 MHz band are 70.1 dBFS and 80.9 dBc, respectively.

Figure 1: Single Channel of Quad IF Receiver Front End (Simplified Schematic: All Connections and Decoupling Not Shown) Gains, Losses, and Signal Levels Measured Values at 10 MHz

CIRCUIT DESCRIPTION

The circuit shown in Figure 1 accepts a single-ended input and converts it to differential using a wide bandwidth (3 GHz) M/A-COM ECT1-1-13M 1:1 transformer. The ADL5565 6.0 GHz differential amplifier has a differential input impedance of 200 Ω when operating at a gain of 6 dB, 100 Ω when operating at a gain of 12 dB, and 67 Ω when operating at a gain of 15.5 dB.

The ADL5565 is an ideal driver for the AD6657A, and the fully differential architecture through the low-pass filter and into the ADC provides good high frequency common-mode rejection, as well as minimizes second-order distortion products. The ADL5565 provides a gain of 6 dB, 12 dB, or 15.5 dB depending on the input connection. In the circuit, a gain of 6 dB was used to compensate for the insertion loss of the filter network and the transformer (approximately 2.1 dB), providing an overall signal gain of 4.0 dB. The gain also helps minimize noise impacts from the amplifier.

The AD6657A is a quad IF receiver where each ADC output is connected internally to a digital noise shaping requantizer (NSR) block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth.

The NSR block can be programmed to provide a bandwidth of either 22%, 33%, or 36% of the sampling rate. For the data taken in this circuit note, the sampling rate was 184.32 MSPS, and the following NSR settings applied:

  • NSR bandwidth = 36%
  • Tuning word (TW) = 12
  • Left band edge = 11.06 MHz (input = 173.26 MHz)
  • Center frequency = 44.24 MHz (input = 140.08 MHz)
  • Right band edge = 77.41 MHz (input = 106.91 MHz)

Details of the operation of the NSR blocks can be found in the AD6657A data sheet.

The anti-aliasing filter is a fourth-order Butterworth low-pass filter designed with a standard filter design program (Agilent ADS in this case). A Butterworth filter was chosen because of its flat response. A fourth order filter yields an ac noise bandwidth ratio of 1.03. Other filter design programs are available from Nuhertz Technologies or Quite Universal Circuit Simulator (Qucs) Simulation.

In order to achieve best performance, the ADL5565 should be loaded with a net differential load of at least 200 Ω. The 20 Ω series resistors isolate the filter capacitance from the amplifier output and, when added with the downstream impedance, yields a net load impedance of 249 Ω.

The 15 Ω resistors in series with the ADC inputs isolate internal switching transients from the filter and the amplifier. The 110 Ω resistors in parallel with the ADC serve to reduce the input impedance of the ADC for more predictable performance.

The differential input impedance of the AD6657A is approximately 2.4 kΩ in parallel with 2.2 pF. The real and imaginary components are a function of input frequency for this type of switched capacitor input ADC; the analysis can be found in Application Note AN-742.

The fourth-order Butterworth filter was designed with a source impedance of 50 Ω, a load impedance of 209 Ω, and a 3 dB bandwidth of 190 MHz. The final circuit values for the filter are shown in Figure 3. The values generated from the filter program are shown in Figure 2. The values chosen for the filter passive components were the closest standard values to those generated by the program. The internal 2.2 pF capacitance of the ADC was utilized as the final shunt capacitance in the filter design. A small amount of additional shunt capacitance (1.5 pF) was added into the final shunt capacitance at the ADC inputs to help reduce kick back charge currents from the ADC input sampling network and to optimize the filter performance.

As seen with this design, obtaining the optimal performance can sometimes be an iterative process. The filter program design values were quite close to the final values, but due to some board parasitics, the final values of the filter were slightly different. Figure 3 shows the final design values for the filter.

Figure 2. Filter Program Initial Design for 4th Order Differential Butterworth Filter with ZS = 50 Ω, ZL = 209 Ω, FC = 190 MHz
Figure 3.Final Design Values for 4th Order Differential Butterworth Filter with ZS = 50 Ω, ZL = 209 Ω, FC = 190 MHz

The measured performance of the system is summarized in Table 1, where the 3 dB bandwidth is 210 MHz. The total insertion loss of the network is approximately 2 dB. The bandwidth response of the final filter circuit is shown in Figure 4, and the SNR, SFDR performance in Figure 5.

Table 1. Measured Performance of the Circuit

Performance Specs @ 1.75 V p-p FS Final Results (kΩ)
Cutoff Frequency (−1dB) 190 MHz
Cutoff Frequency (−3dB) 210 MHz
Passband Flatness (10MHz to 190MHz) 1 dB
SNRFS @ 140MHz 70.1 dBFS
SFDR @ 140MHz 80.9 dBc
H2 / H3 @ 140MHz 97.7 / 80.9 dBc
Overall Gain @ 10MHz 3.9dB
Input Drive @ 10MHz 4.9 dBm

Figure 4. Pass-Band Flatness Performance vs. Input Frequency
Figure 5. SNR/SFDR Performance vs. Input Frequency

FILTER AND INTERFACE DESIGN PROCEDURE

In this section, a general approach to the design of the amplifier/ADC interface with filter is presented. In order to achieve optimum performance (bandwidth, SNR, SFDR, etc.), there are certain design constraints placed on the general circuit by the amplifier and the ADC:

  • The amplifier should see the correct dc load recommended by the data sheet for optimum performance.
  • The correct amount of series resistance must be used between the amplifier and the load presented by the filter. This is to prevent undesired peaking in the pass band.
  • The input to the ADC should be reduced by an external parallel resistor, and the correct series resistance should be used to isolate the ADC from the filter. This series resistor also reduces peaking.

This design approach will tend to minimize the insertion loss of the filter by taking advantage of the relatively high input impedance of most high speed ADCs and the relatively low impedance of the driving source.

Details of the design procedure can be found in Circuit Notes CN-0227 and CN-0238.

CIRCUIT OPTIMIZATION TECHNIQUES AND TRADEOFFS

The parameters in this interface circuit are very interactive; therefore. it is almost impossible to optimize the circuit for all key specifications (bandwidth, bandwidth flatness, SNR, SFDR, gain, etc.). However, the peaking which often occurs in the bandwidth response can be minimized by varying RA and RKB.

The series resistor on the ADC inputs (RKB ) should be selected to minimize distortion caused by any residual charge injection from the internal sampling capacitor within the ADC. Increasing this resistor also tends to reduce bandwidth peaking.

However, increasing RKB increases signal attenuation, and the amplifier must drive a larger signal to fill the ADC input range.

Another method for optimizing the passband flatness is to vary the filter shunt capacitor by a small amount.

The ADC input termination resistor (2RTADC) should normally be selected to make the net ADC input impedance between 200 Ω and 400 Ω. Making it lower reduces the effect of the ADC input capacitance and may stabilize the filter design, but increases the insertion loss of the circuit. Increasing the value will also reduce peaking.

Balancing these trade-offs can be somewhat difficult. In this design, each parameter was given equal weight; therefore, the values chosen are representative of the interface performance for all the design characteristics. In some designs, different values might be chosen to optimize SFDR, SNR, or input drive level, depending on system requirements.

The SFDR performance in this design is determined by two factors: the amplifier and the ADC interface component values, as shown in Figure 1. The final SFDR performance numbers shown in Table 1 and Figure 5 were obtained after optimizing the filter design to account for the board parasitics and nonideal components used in the filter design.

Another trade-off that can be made in this particular design is the ADC full-scale setting. The full-scale ADC differential input voltage was set for 1.75 V p-p for the data obtained with this design, which optimizes SFDR. Changing the full-scale input range to 2.0 V p-p yields a small improvement in SNR, but slightly degrades the SFDR performance. Changing the fullscale input range in the opposite direction to 1.5 V p-p yields a small improvement in SFDR but slightly degrades the SNR performance.

Note that the signal in this design is ac coupled with the 0.1 µF capacitors to block the common-mode voltages between the amplifier, its termination resistors, and the ADC inputs. Please refer to the AD6657A data sheet for further details regarding common-mode voltages.

PASSIVE COMPONENT AND PC BOARD PARASITIC CONSIDERATIONS

COMMON VARIATIONS

For applications that require less bandwidth and lower power, the ADL5562 differential amplifier can be used. The ADL5562 has a bandwidth of 3.3 GHz. For even lower power and bandwidth, the ADA4950-1 could also be used. This device has a 1 GHz bandwidth and only uses 10 mA of current.

CIRCUIT EVALUATION AND TEST

This circuit uses the EVAL-CN0259-HSCZ circuit board and the HSC-ADC-EVALCZ FPGA-based data capture board. The two boards have mating high speed connectors, allowing for the quick setup and evaluation of the circuit's performance. The EVAL-CN0259-HSCZ board contains the circuit evaluated as described in this note, and the HSC-ADC-EVALCZ data capture board is used in conjunction with Visual Analog evaluation software, as well as the SPI Controller software to properly control the ADC and capture the data. See the CN0259 Design Support package for the schematic, BOM, and layout files for the EVAL-CN0259-HSCZ board. Application Note AN-835 contains complete details on how to set up the hardware and software to run the tests described in this circuit note.

SAMPLE PRODUCTS USED IN THIS CIRCUIT

Product Description Available Product Models to Sample
AD6657A 65MHz Bandwidth Quad IF Receiver

To obtain samples of this part, please contact ADI

ADL5565 6 GHz Ultrahigh Dynamic Range Differential Amplifier ADL5565ACPZ-R7
Evaluation Hardware
Boards checked are needed to evaluate this circuit.
Model Description Price RoHS Check Inventory/
Purchase/Sample
EVAL-CN0259-HSCZ High Performance 65 MHz Bandwidth Quad IF Receiver with Antialiasing Filter and 184.32 MSPS Sampling Rate $385.00 Yes
HSC-ADC-EVALCZ High Speed Eval Control Board $607.20 Yes
Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.
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