In applications where the DAC output voltage range is required to be larger than the input voltage, a programmable gain circuit can be used. This circuit provides a programmable gain function using a multiplying DAC, the AD5450/AD5451/ AD5452/AD5453, and a fast, low offset operational amplifier, the AD8065. The maximum gain value and the temperature coefficient are set by external resistors, and the resolution of the programmable gain is set by the resolution of the DAC.
Figure 1. Programmable Gain Circuit Using a Current Output DAC (Simplified Schematic: Decoupling and All Connections Not Shown)
The circuit shown in Figure 1 is the recommended method of increasing the gain of the circuit. R1, R2, and R3 should all have similar temperature coefficients, but they need not match the temperature coefficients of the DAC. This approach is recom-mended in circuits where gains of greater than 1 are required.
where D is the digital word loaded to the DAC. D = 0 to 255 (8-bit AD5450), D = 0 to 1023 (10-bit AD5451), D = 0 to 4095 (12-bit AD5452), D = 0 to 16383 (14-bit AD5453); N is the number of bits.
The key benefit of this circuit is its ability to overcome gain TC errors using resistor matching. The TC of the external resistors needs to match each other but do not need to match that of the DAC internal ladder resistance.
Resistor R1 is required because R1 plus the input impedance of the DAC must equal the total feedback resistance which is RFB plus R2||R3. The input impedance of the DAC is RFB, so
The values of R1 and R2 must be chosen such that the output voltage does not exceed the output range of the operational amplifier for the given supply voltage. Also note that the bias current of the operational amplifier is multiplied by the total feedback resistance (RFB + R2||R3) to give an associated offset. Thus, the values of R1 and R2 cannot be too large or they will have a significant effect on the overall offset voltage.
The AD5450/AD5451/AD5452/AD5453 products are designed on a 5 V CMOS process and operate from a VDD1 power supply of 2.5 V to 5.5 V. The output amplifier is driven from a dual power supply voltage (VDD/VSS), which needs to be large enough to accommodate the analog output range of the circuit. Generally, ±12 V supplies are sufficient. The 4.7 pF capacitor is used to prevent ringing or instability in the closed-loop application.
The input offset voltage of an op amp is multiplied by the variable noise gain (due to the code-dependent output resistance of the DAC) of the circuit. A change in this noise gain between two adjacent digital codes produces a step change in the output voltage due to the amplifier’s input offset voltage. This output voltage change is superimposed on the desired change in output between the two codes and produces a diffe-rential linearity error, which if large enough, could cause the DAC to be non-monotonic. The AD8065 benefits from both a low input offset voltage and low bias currents to overcome this issue.
The OP1177 is another excellent op amp candidate for the I-V conversion circuit. It also provides low offset voltage and ultralow bias current. For the selection of the reference, the input voltage is restricted by the rail-to-rail voltage of the operational amplifier selected and also the gain set up by the resistors R2 and R3.