This circuit is a bipolar, precision DAC configuration that employs an AD5450/AD5451/AD5452/AD5453 precision multiplying DAC and the AD8066 low-noise op-amp. The DAC is the core-programmable element, and the amplifier selection dictates the performance in terms of precision or speed. For an accurate, high precision, low noise application, a dual opera-tional amplifier (op amp) such as the AD8066 can be used to provide the current-to-voltage conversion and the signal conditioning. A low noise reference such as ADR01 is required to drive the VREF input and the optimum output noise performance is obtained by using a low noise low bandwidth output amplifier. The main advantages of this circuit are simplicity, constant reference input impedance, and the ability of VREF to exceed the DAC VDD supply voltage.
Figure 1: Bipolar Precision DC Conversion (Simplified Schematic: Decoupling and All Connections Not Shown)
In many applications, it may be necessary to generate a full four-quadrant multiplying operation or a bipolar output voltage swing as shown in Figure 1. This can be easily accomplished by using a dual amplifier denoted by A1 and A2 and some external resistors. In this circuit, the A1 amplifier performs the current-to-voltage conversion, and the second amplifier, A2, provides a gain of 2. Biasing the external amplifier with an offset from the reference voltage results in a full four-quadrant multiplying operation. In dc applications, a suitable reference to drive the reference input is the ADR01. This is a high accuracy, high stability, 10 V precision voltage reference. Because voltage reference temperature coefficient and long-term drift are primary considerations for applications requiring high precision conversion, this device is an ideal candidate.
The AD5450/AD5451/AD5452/AD5453 DACs are designed on a 5 V CMOS process and operate from a VDD power supply of 2.5 V to 5.5 V. They accept VREF input ranges of up to 10 V as shown in Figure 1, and the power supply for the output amplifiers must be a bipolar supply with enough headroom to accommodate the analog output range, VOUT. The transfer function of this circuit shows that both negative and positive output voltages are created as the input code, D, is incremented from Code 0 (VOUT = − VREF) to midscale (VOUT = 0 V ) to full-scale (VOUT = +VREF). VOUT is represented by the following equation:
VOUT = VREF x (D/2N-1) – VREF.
N is the resolution of the DAC.
D is the digital word loaded to the DAC ,and D = 0 to 255 (8-bit AD5450), D = 0 to 1023 (10-bit AD5451), D = 0 to 4095 (12-bit AD5452), or D = 0 to 16,383 (14-bit AD5453).
An op amp is used in the current-to-voltage (I-V) stage of this circuit. The supply voltage of the op amp limits the reference voltage that can be used with the DAC. An op-amp’s bias current and offset voltage are both important selection criteria for precision current output DACs. Therefore, this circuit employs the AD8066 op amp, which has ultralow offset voltage (0.4 mV typical) and bias current (2 pA typical).
The input offset voltage of an op amp is multiplied by the variable noise gain (due to the code-dependent output resistance of the DAC) of the circuit. A change in this noise gain between two adjacent codes produces a step change in the output voltage due to the amplifier’s input offset voltage. This output voltage change is superimposed on the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, can cause the DAC to be nonmonotonic.
In general, the input offset voltage should be a fraction of an LSB to ensure monotonic behavior when stepping through codes. A compensation capacitor, C1, is used to prevent ringing or instability in the closed loop. Typical values in the 1 pF to 5 pF range can be used.
In any circuit where accuracy is important, careful consider-ation of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the DAC is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device.
These DACs should have ample supply bypassing of 10 μF in parallel with 0.1 μF on the supply located as close to the package as possible, ideally right up against the device. The 0.1 μF capacitor should have low effective series resistance (ESR) and low effective series inductance (ESL), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching.
Low ESR, 1 μF to 10 μF tantalum capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. To optimize high frequency performance, the I-V amplifier should be located as close to the DAC as possible.
The OP2177 is another excellent dual op-amp candidate for the I-V conversion circuit. It also provides a low offset voltage (15 μV typical) and ultralow bias current (0.5 nA typical). The ADR02 and ADR03 with 5.0 V and 2.5 V output, respectively, are other low noise references available from the same reference family as the ADR01. Other low noise references that are suitable are the ADR441 and ADR445. The size of the reference input voltage is restricted by the rail-to-rail voltage of the operational amplifier selected.