Applies to the following video encoders ...
Introduction ...
A defined power supply sequence is mandatory for the ADV734x range of video encoders. This is required to ensure the correct reset sequence for the device. Failure to carry out this sequence may cause incorrect operation of the device.
Symptoms ...
- I2C communication Failure
- No Acknowledge of Slave Address
Problem sequence ...
Any sequence whereby the VDD supply is established before VDDIO may cause the power supply sequencing issue to occur. When this sequence occurs, the digital core may go in to SPI mode of operation therefore I2C communication is not possible.
Solution ...
The VDDIO and VDD power supplies should be sequenced as described in Figure 1.
VDDIO must be established before VDD.
VAA and VPLL
The VAA and VPLL power supplies do not play a part in the power supply sequencing issue. These can be powered up in any order. All sequences with VDDIO established 250µSec before VDD are robust.
Circuit suggestions ...
If there is no power supply sequencing capability in the design, the following suggestions may be an option.
- Power supplies often have large reservoir capacitors on each power supply. Increasing Capacitance on the VDD supply will result in slowing down VDD allowing VDDIO to establish itself first.
- Conversely, reducing VDDIO capacitance will enable it to rise faster in advance of the VDD supply.
When increasing capacitance on the VDD power supply, a bleed resistor of approx 1.5K should be connected from the CAP +. This allows the Capacitor to discharge when the circuit is powered down.
Discharging the capacitor to below 0.7 volts is required for the Power-on-RESET circuit to issue a reset to the chip on the next powering up of the encoder.
