Oscilloscopes and Digitizers
The AD9208 is a dual, 14-bit, 3 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and- hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The −3 dB bandwidth of the ADC input is 9 GHz. The AD9208 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and up to four half-band decimation filters. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9208 between the DDC modes is selectable via SPI-programmable profiles.
In addition to the DDC blocks, the AD9208 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9208 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.
The user can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, four- lane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF± and SYNCINB± input pins.
The AD9208 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI).
The AD9208 is available in a Pb-free, 196-ball BGA, specified over the −40°C to +85°C ambient temperature range. This product is protected by a U.S. patent.
Note that throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.
- Wide, input −3 dB bandwidth of 9 GHz supports direct radio frequency (RF) sampling of signals up to about 5 GHz.
- Four integrated, wideband decimation filter and NCO blocks supporting multiband receivers.
- Fast NCO switching enabled through GPIO pins.
- A SPI controls various product features and functions to meet specific system requirements.
- Programmable fast overrange detection and signal monitoring.
- On-chip temperature dioide for system thermal management.
- 12mm × 12mm 196-Lead BGA
- Diversity multiband, multimode digital receivers
- 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A
- Electronic test and measurement systems
- Phased array radar and electronic warfare
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
- Wireless Infrastructure
- Wideband RF Signal Processing
- Software Defined Radio
High Speed Converters
The AD9684 is a dual, 14-bit, 500 MSPS ADC. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9684 is optimized for wide input bandwidth, a high sampling rate, excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs, supporting a variety of user selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate by 2 block.
The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO), and three half-band decimation filters supporting a divide by factor of two, four, and eight.
- Diversity multi-band, multi-mode digital receivers
3G/4G, TD-SCDMA, WCDMA, MC-GSM, LTE
- General-purpose software radios
- Ultrawideband satellite receiver
- Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions)
- Digital oscilloscopes
- High speed data acquisition systems
- DOCSIS CMTS upstream receive paths
- HFC digital reverse path receivers
The AD5624R/AD5644R/AD5664R have an on-chip reference. The AD56x4R-3 has a 1.25 V, 5 ppm/°C reference, giving a full-scale output range of 2.5 V; the AD56x4R-5 has a 2.5 V, 5 ppm/°C reference giving a full-scale output range of 5 V. The on-chip reference is off at power-up, allowing the use of an external refer-ence; all devices can be operated from a single 2.7 V to 5.5 V supply. The internal reference is enabled via a software write.
The part incorporates a power-on reset circuit that ensures the DAC output powers up to 0 V and remains there until a valid write takes place. The part contains a per-channel power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in power-down mode. The low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment.
The AD5624R/AD5644R/AD5664R use a versatile 3-wire serial interface that operates at clock rates up to 50 MHz, and is compatible with standard SPI, QSPI™, MICROWIRE™, and DSP interface standards. The on-chip precision output amplifier enables rail-to-rail output swing.
- Quad 12-/14-/16-bit DACs.
- On-chip 1.25 V/2.5 V, 5 ppm/°C reference.
- Available in 10-lead MSOP and 10-lead, 3 mm × 3 mm, LFCSP_WD.
- Low power, typically consumes 1.32 mW at 3 V and 2.25 mW at 5 V.
- Process controls
- Data acquisition systems
- Portable battery-powered instruments
- Digital gain and offset adjustment
- Programmable voltage and current sources
- Programmable attenuators
The ADA4817-1 (single) and ADA4817-2 (dual) FastFET™ amplifiers are unity-gain stable, ultrahigh speed, voltage feedback amplifiers with FET inputs. These amplifiers were developed with the Analog Devices, Inc., proprietary eXtra fast complementary bipolar (XFCB) process, which allows the amplifiers to achieve ultralow noise (4 nV/√Hz; 2.5 fA/√Hz) as well as very high input impedances.
With 1.3 pF of input capacitance, low noise (4 nV/√Hz), low offset voltage (2 mV maximum), and 1050 MHz −3 dB bandwidth, the ADA4817-1/ADA4817-2 are ideal for data acquisition front ends as well as wideband transimpedance applications, such as photodiode preamps.
With a wide supply voltage range from 5 V to 10 V and the ability to operate on either single or dual supplies, the ADA4817-1/ADA4817-2 are designed to work in a variety of applications including active filtering and ADC driving.
The ADA4817-1 is available in a 3 mm × 3 mm, 8-lead LFCSP and 8-lead SOIC, and the ADA4817-2 is available in a 4 mm × 4 mm, 16-lead LFCSP. These packages feature a low distortion pinout that improves second harmonic distortion and simplifies circuit board layout. They also feature an exposed paddle that provides a low thermal resistance path to the printed circuit board (PCB). This enables more efficient heat transfer and increases reliability. These products are rated to work over the extended industrial temperature range (−40°C to +105°C).
- Photodiode amplifiers
- Data acquisition front ends
- ADC drivers
- Output buffers
Security and Surveillance
- Scanning Equipment
The ADA4930-1/ADA4930-2 are very low noise, low distortion, high speed differential amplifiers. They are an ideal choice for driving 1.8 V high performance ADCs with resolutions up to 14 bits from dc to 70 MHz. The adjustable output common mode allows the ADA4930-1/ADA4930-2 to match the input of the ADC. The internal common-mode feedback loop provides exceptional output balance, suppression of even-order harmonic distortion products, and dc level translation.
With the ADA4930-1/ADA4930-2, differential gain configurations are easily realized with a simple external feedback network of four resistors determining the closed-loop gain of the amplifier.
The ADA4930-1/ADA4930-2 are fabricated using Analog Devices, Inc., proprietary silicon-germanium (SiGe), complementary bipolar process, enabling them to achieve very low levels of distortion with an input voltage noise of only 1.2 nV/√Hz.
The low dc offset and excellent dynamic performance of the ADA4930-1/ADA4930-2 make them well suited for a wide variety of data acquisition and signal processing applications.
The ADA4930-1 is available in a Pb-free, 3 mm × 3 mm 16-lead LFCSP, and the ADA4930-2 is available in a Pb-free, 4 mm × 4 mm 24-lead LFCSP. The pinout has been optimized to facilitate printed circuit board (PCB) layout and minimize distortion. The ADA4930-1 is specified to operate over the −40°C to +105°C temperature range, and the ADA4930-2 is specified to operate over the −40°C to +105°C temperature range for 3.3 V or 5 V supply voltages.
- ADC drivers
- Single-ended-to-differential converters
- IF and baseband gain blocks
- Differential buffers
- Line drivers
- Life Sciences & Medical Instrumentation
Interactive Signal Chains