Head Units and Cluster
The ADV7613 is a high quality, low power, single-input HDMI to LVDS display bridge. It incorporates an HDMI capable receiver that supports up to 1080p, 60 Hz.
The HDMI port has dedicated 5 V detect and hot plug assert pins. The HDMI receiver also includes an integrated equalizer that ensures the robust operation of the interface with long cables.
The ADV7613 has an audio output port for the audio data extracted from the HDMI stream. HDMI audio formats include super audio CD (SACD) via Direct Stream Digital® (DSD) and HBR. The HDMI receiver has an advanced mute controller that prevents audible extraneous noise in the audio output.
The ADV7613 contains a component processor (CP) that processes the video signals from the HDMI receiver. It provides features such as contrast, brightness and saturation adjustments, STDI detection block, free run, and synchronization alignment controls.
The LVDS encoder can package data into 6-bit or 8-bit non-dc balanced OpenLDI mapping or 8-bit VESA mapping. The ADV7613 can output 24-bit OpenLDI data via dual-channel LVDS transmitters, up to a maximum resolution of 1080p, 60 Hz received at the input. The maximum output clock supported by a single LVDS output port is 92 MHz.
The ADV7613 is offered in an automotive grade and a consumer grade. The operating temperature range is −40°C to +85°C.
Fabricated in an advanced CMOS process, the ADV7613 is provided in a 9 mm × 9 mm, 100-ball CSP_BGA, RoHS-compliant package.
- Automotive infotainment headunits
- Automotive infotainment displays
- Digital signage
The ADSP-SC57x/ADSP-2157x processors are members of the SHARC® family of products. The ADSP-SC57x processor is based on the SHARC+® dual-core and the ARM® Cortex®-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.
By integrating a set of industry leading system peripherals and memory, the ARM Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.
The ADAU1462/ADAU1466 are automotive qualified audio processors that far exceed the digital signal processing capabilities of earlier SigmaDSP® devices. They are pin and register compatible with each other, as well as with the ADAU1450/ADAU1451/ADAU1452 SigmaDSP processors. The restructured hardware architecture is optimized for efficient audio processing. The audio processing algorithms support a seamless combination of stream processing (sample by sample), multirate processing, and block processing paradigms. The SigmaStudio™ graphical programming tool enables the creation of signal processing flows that are interactive, intuitive, and powerful. The enhanced digital signal processor (DSP) core architecture enables some types of audio processing algorithms to be executed using significantly fewer instructions than were required on previous SigmaDSP generations, leading to vastly improved code efficiency.
The 1.2 V, 32-bit DSP core can run at frequencies of up to 294.912 MHz and execute up to 6144 SIMD instructions per sample at the standard sample rate of 48 kHz. Powerful clock generator hardware, including a flexible phase-locked loop (PLL) with multiple fractional integer outputs, supports all industry standard audio sample rates. Nonstandard rates over a wide range can generate up to 15 sample rates simultaneously. These clock generators, along with the on board asynchronous sample rate converters (ASRCs) and a flexible hardware audio routing matrix, make the ADAU1462/ADAU1466 ideal audio hubs that greatly simplify the design of complex multirate audio systems.
The ADAU1462/ADAU1466 interface with a wide range of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), digital audio devices, amplifiers, and control circuitry with highly configurable serial ports, I2C, serial peripheral interface (SPI), Sony/Philips Digital Interconnect Format (S/PDIF) interfaces, and multipurpose input/output (I/O) pins. Dedicated decimation filters can decode the pulse code modulation (PDM) output of up to four MEMS microphones.
Independent slave and master I2C/SPI control ports allow the ADAU1462/ADAU1466 to be programmed and controlled by an external master device such as a microcontroller, and to program and control slave peripherals directly. Self boot functionality and the master control port enable complex standalone systems.
The power efficient DSP core can execute at high computational loads while consuming only a few hundred milliwatts (mW) in typical conditions. This relatively low power consumption and small footprint make the ADAU1462/ADAU1466 ideal replacements for large, general-purpose DSPs that consume more power at the same processing load.
- Automotive audio processing
- Head units
- Distributed amplifiers
- Rear seat entertainment systems
- Trunk amplifiers
- Commercial and professional audio processing
The ADV7282A has the same pinout as and is software compatible with the ADV7282. The mobile industry processor interface (MIPI®) model of the ADV7282A (ADV7282A-M) has the same pinout as and is software compatible with the ADV7282-M.
All features, functionality, and specifications are shared by the ADV7282A and the ADV7282A-M, unless otherwise noted.
The ADV7282A is a versatile one-chip, multiformat video decoder that automatically detects standard analog baseband video signals and converts them into YCrCb 4:2:2 component video data streams.
The analog input of the ADV7282A features an input mux (4-channel on ADV7282A, 6-channel on ADV7282A-M), a single 10-bit analog-to-digital converter (ADC) and an on-chip differential to single-ended converter to accommodate the direct connection of differential, pseudo differential, or single-ended CVBS without the need for external amplifier circuitry.
The standard definition processor (SDP) in the ADV7282A automatically detects PAL, NTSC and SECAM standards in the form of composite, S-Video (Y/C) and component. The analog video is converted into a 4:2:2 component video data stream that is output either via an 8-bit ITU-R BT.656 standard-compatible interface (ADV7282A) or via a MIPI CSI-2 Tx (hereafter referred to as MIPI Tx) interface (ADV7282A-M). The ADV7282A also feature a deinterlacer for interlaced to progressive (I2P) conversion.
The ADV7282A offers short to battery (STB) diagnostic sense inputs and general-purpose outputs.
The ADV7282A is provided in a space-saving LFCSP surface-mount, RoHS compliant package. The ADV7282A is rated over the −40°C to +105°C temperature range, making it ideal for automotive applications.
The ADV7282A must be configured in accordance with the I2C writes provided in the evaluation board script files.
- Advanced driver assistance
- Automotive infotainment
- DVRs for video security
- Media players
The ADV7481 MHL 2.1 capable receiver supports a maximum pixel clock frequency of 75 MHz, allowing resolutions up to 720p/1080i at 60 Hz in 24-bit mode. The ADV7481 features a link control bus (CBUS) that handles the link layer, translation layer, CBUS electrical discovery, and display data channel (DDC) commands. The implementation of the MHL sideband channel (MSC) commands by the system processor can be handled either by the I2C bus, or via a dedicated serial peripheral interface (SPI) bus. A dedicated interrupt pin (INTRQ3) is available to indicate that events related to CBUS have occurred.
The ADV7481 also features an enable pin (VBUS_EN) to dynamically enable or disable the output of a voltage regulator, which provides a 5 V voltage bus (VBUS) signal to the MHL source.
The ADV7481 HDMI capable receiver supports a maximum pixel clock frequency of 162 MHz, allowing HDTV formats up to 1080p, and display resolutions up to UXGA (1600 × 1200 at 60 Hz). The device integrates a consumer electronics control (CEC) controller that supports the capability discovery and control (CDC) feature. The HDMI input port has dedicated 5 V detect and Hot Plug™ assert pins.
The HDMI/MHL receiver includes an adaptive transition minimized differential signaling (TMDS) equalizer that ensures robust operation of the interface with long cables.
The ADV7481 single receiver port is capable of accepting both HDMI and MHL electrical signals. Automatic detection between HDMI and MHL is achieved by using cable impedance detection through the CD_SENSE pin.
The ADV7481 contains a component processor (CP) that processes the video signals from the HDMI/MHL receiver. It provides features such as contrast, brightness, and saturation adjustments, as well as free run and timing adjustment controls for HS/VS/DE timing.
The ADV7481 analog front end (AFE) comprises a single high speed, 10-bit analog-to-digital converter (ADC) that digitizes the analog video signal before applying it to the SDP.
The eight analog video inputs can accept single-ended, pseudo differential, and fully differential composite video signals, as well as S-Video and YPbPr video signals, supporting a wide range of consumer and automotive video sources.
Short to battery (STB) events can be detected on differential input video signals. STB protection is provided by ac coupling the input video signals. The ADV7481, in combination with an external resistor divider, provides a common-mode input range of 4 V, enabling the removal of large signal common-mode transients present on the video lines.
The automatic gain control (AGC) and clamp restore circuitry allow an input video signal up to 1.0 V p-p at the analog video input pins of the ADV7481. Alternatively, the AGC and clamp restore circuitry can be bypassed for manual settings.
The SDP of the ADV7481 is capable of decoding a large selection of analog baseband video signals in composite, S-Video, and component formats. The SDP supports worldwide NTSC, PAL, and SECAM standards.
The ADV7481 features an 8-bit digital input/output port, supporting input and output video resolutions up to 720p/1080i in both the 8-bit interleaved 4:2:2 SDR and DDR modes.
- Portable devices
- Automotive infotainment (head unit and rear seat
- HDMI repeaters and video switches
Interactive Signal Chains
Product Selection Guide