The AD9248 is a dual, 3 V, 14-bit, 20/40/65 MSPS analog to digital converter. It features dual high performance sample-and-hold amplifiers and an integrated voltage reference. The AD9248 uses a multistage differential pipelined architecture with output error correction logic to provide 14-bit accuracy and guarantee no missing codes over the full operating temperature range at up to 65 MSPS data rates.
The wide bandwidth, differential SHA allows for a variety of user-selectable input ranges and offsets including single-ended applications. It is suitable for various applications including multiplexed systems that switch full-scale voltage levels in successive channels and for sampling inputs at frequencies well beyond the Nyquist rate. The AD9248 is suitable for applications in communications, imaging and medical ultrasound.
Dual single-ended independent clock inputs are used to control all internal conversion cycles. A Duty Cycle Stabilizer (DCS) is available on the AD9248-65 and can compensate for wide variations in the clock duty cycle, allowing the converters to maintain excellent performance. The digital output data is presented in either straight binary or twos complement format. Out-of-range signals indicate an overflow condition, which can be used with the most significant bit to determine low or high overflow.
Fabricated on an advanced CMOS process, the AD9248 is available in a space saving 64-pin LQFP and is pin compatible to the AD9238. It is specified over the industrial temperature range (-40°C to +85°C).
|Title||Content Type||File Type|
|AD9248: 14-Bit, 20 MSPS/40 MSPS/65 MSPS Dual A/D Converter Data Sheet (Rev B, 11/2010) (pdf, 1719 kB)||Data Sheets|
|ADW12001: 14-Bit, 40 MSPS Dual Analog-to-Digital Converter Data Sheet (Rev 0, 01/2009) (pdf, 662 kB)||Data Sheets|
|AN-1142: Techniques for High Speed ADC PCB Layout (pdf, 392 kB)||Application Notes|
|AN-282: Fundamentals of Sampled Data Systems (pdf, 2131 kB)||Application Notes|
|AN-737: How ADIsimADC Models an ADC (pdf, 373 kB)||Application Notes|
|AN-807: Multicarrier WCDMA Feasibility (pdf, 969 kB)||Application Notes|
AN-808: Multicarrier CDMA2000 Feasibility
(pdf, 1535 kB)
The goal of this application note is to determine the feasibility of implementing a multicarrier CDMA2000 transceiver and what the major subsystem performances must be.
|AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (pdf, 203 kB)||Application Notes|
|AN-905: VisualAnalog Converter Evaluation Tool Version 1.0 User Manual (pdf, 2124 kB)||Application Notes|
|AN-935: Designing an ADC Transformer-Coupled Front End (pdf, 363 kB)||Application Notes|
|AN-835: Understanding High Speed ADC Testing and Evaluation (pdf, 985 kB)||Application Notes|
|AN-803: Pin Compatible High Speed ADCs Simplify Design Tasks (pdf, 356 kB)||Application Notes|
|AN-742: Frequency Domain Response of Switched-Capacitor ADCs (pdf, 401 kB)||Application Notes|
|AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated (pdf, 370 kB)||Application Notes|
AN-345: Grounding for Low-and-High-Frequency Circuits
(pdf, 455 kB)
Know Your Ground and Signal Paths for Effective Designs. Current Flow Seeks Path of Least Impedance-Not Just Resistance....
|AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (pdf, 291 kB)||Application Notes|
AN-501: Aperture Uncertainty and ADC System Performance
(pdf, 227 kB)
A Key Concern in IF Sampling is that of Aperture Uncertainty (Jitter)
|CN-0320: An IQ Demodulator-Based IF-to-Baseband Receiver with IF and Baseband Variable Gain and Programmable Baseband Filtering, and Dual ADC (pdf, 248 kB)||Circuit Note|
|UG-173: High Speed ADC USB FIFO Evaluation Kit (HSC-ADC-EVALB-DCZ) (pdf, 774 kB)||User Guides|
|MS-2210: Designing Power Supplies for High Speed ADC (pdf, 327 kB)||Technical Articles|
Buffer Adapts Single-ended Signals for Differential Inputs
by Randall Carver, Analog Devices (EDN Design Idea, 9/2/2004)
|Flow Cytometry Blood Analysis Systems||Technical Articles||HTML|
Correlating High-Speed ADC Performance to Multicarrier 3G Requirements
by Brad Brannon (RF Design, 6/1/2003)
Matching An ADC To A Transformer
by Rob Reeder, Analog Devices, Inc.
(Microwaves & RF, 7/2007)
|RAQs index||Rarely Asked Questions||HTML|
|Glossary of EE Terms||Glossary||HTML|
|Title||Content Type||File Type|
ADIsimADC is Analog Devices' Analog-to-Digital Behavioral Model that accurately models the typical performance characteristics of many of our High Speed Converters. The model faithfully reproduces the errors associated with both static and dynamic features such as AC linearity, clock jitter, and many other product specific anomalies.
|ADIsim Design/Simulation Tools||HTML|
|AD9248 IBIS Models||IBIS Models||HTML|
Recommended ADC Drivers for the AD9248
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