Programming the Post Processor
The post processor is programmed by loading user-defined filter data in the form of a configuration file into the device.
Generating a Configuration File to Load into the Post Processor
A user-defined configuration file can be generated to load into the post processor on the AD7725 to program the multipliers and accumulators to perform user-specific filtering requirements. This file is generated using a digital filter design package called Filterwizard which can be downloaded from the Development Kit link on this site.
For evaluation purposes, the AD7725 has an internal default filter stored in ROM which can be loaded into the post processor. This functionality allows the user to evaluate the device without having to download an external configuration file.
The bit stream of data from the preset filter is available to the post processor at a frequency of CLKIN/8. Due to the nature of the design of the post processor, there is an unavoidable minimum decimate by two resulting in the maximum output data rate of any filter being CLKIN/16.
The filter can be either FIR or IIR in design. FIR filters are inherently stable and have linear phase, however they are computationally inefficient and require more coefficients for a given roll off compared with IIR Filters. IIR filters have the disadvantage of being potentially unstable and having non-linear phase.
The maximum number of taps available to be used in the post processor is 108. Therefore, a single filter with 108 taps can be designed or a multi-stage filter can be designed where the total number of taps adds up to 108.
Filter Design Factors - Using your taps
(i)Stop band Attenuation and Transition width
In filter design, it is desirable to have a large stop band attenuation and a narrow filter transition width. To achieve both of these requires a large amount of filter taps. Therefore some compromises have to be made during the design to be able to optimize the amount of taps used. There is usually a trade off of stop band attenuation for transition width or vice versa. An example is, a filter with a cut off frequency of 100kHz which rolls off between 100kHz and 200kHz uses less taps than a filter with a cutoff frequency of 100 kHz which rolls off between 100 kHz and 150 kHz. To reduce the number of taps used to achieve a certain specification, a multi-stage filter can be designed that performs decimation between stages. The first filter stage can be used to perform decimation and as a pre-filter to remove out of band noise, then the subsequent stages can have more stringent specifications.
Decimation reduces the output data rate of the filter, resulting in lower input data rates for subsequent filter stages. For FIR filters, if a filter is designed for an input data rate of half the maximum data rate i.e. the previous filter stage had decimation by two, the filter can obtain half the transition width of a filter designed for the maximum input data rate for a given number of taps. An example is, the number of taps required to generate a filter with a cutoff frequency of 100kHz and a stop band frequency of 200kHz will equal the number of taps required to generate a filter with a cutoff frequency of 100kHz and a stop band frequency of 150kHz if the data stream is decimated by two prior to the filtering stage.
For IIR filters, decimation has no effect on the transition width.
When decimation is performed, the amount of filter coefficients required to achieve certain filter specifications is reduced resulting in a reduction in the power dissipation of the device to realize the filter. Therefore, if a one-stage filter meets the roll off and stop band attenuation requirements of the application, but is dissipating more power than is acceptable, then decimation will be a solution here.
Filter Design Example
This filter design example shows the benefits of using a 2-stage filter with a half band filter performing decimation in the first stage. The filter designed is for an application operating with a CLKIN of 9.6MHz and that requires a low pass FIR filter with a cutoff frequency of 50kHz and a stop-band frequency of 100kHz, a pass-band ripple of 0.01dB and a stop-band attenuation of 120dB. To generate this filter in a single stage requires 189 coefficients, which exceeds the maximum filter coefficients of the device. If the transition width of 50kHz and the pass-band and stop-band ripple and attenuation specifications are essential, a two-stage filter can be designed with decimation.
The first stage is a simple half-band filter with a bandwidth of fs/4 and a wide transition width. If a 9.6MHz clock frequency is used, the bandwidth of the half-band filter will be 300 kHz. With a half-band filter, all the odd coefficients except the middle coefficient are zero. The post processor therefore only has to process the odd data stream until it finds a non-zero coefficient. This stage is used to remove out of band quantization noise that will wrap into the band of interest when the data-stream is decimated. This stage also performs post-filtering decimation by four so that the input to the second stage is CLKIN/32.
Figure 1 shows the response of this half band filter.
Figure 1. Half Band Filter Response
After filtering in stage one, the data stream is decimated by four so the input data rate to stage two is CLKIN/32 or 300kHz. A narrower transition width is required in stage two. This is now possible, as due to decimation in stage one, less taps are required to achieve the narrow transition width. Therefore, with a cutoff frequency of 50kHz and a stop-band frequency of 100kHz, the number of taps used in this stage is now 49, resulting the total number of taps used for the filter response being 74. These figures are now within the maximum specifications of the device. Figure 2 shows the response of the two-stage low pass filter.
Figure 2. Two-Stage Low Pass Filter Response