Block Diagram of the AD7725 Modulator and Filter Layout

Figure 1 Block Diagram of the AD7725 Modulator and Filter Layout

The AD7725 employs a sigma-delta conversion technique to convert the analog input into an equivalent digital word. The Modulator samples the analog input at the CLKIN frequency. Due to its high over-sampling rate the quantisation noise is spread from 0 to CLKIN/2 thus reducing the noise in the band of interest. The modulator also shapes the noise, pushing most of it out of the bandwidth of interest.

The Preset Filter follows the modulator and this had a fixed response. It consists of 3 half band FIR filters and each of these decimate by two, providing a CLKIN/8 data rate to the programmable Post Processor. The main function of the Preset filter is to remove the out of band quantisation noise and reduce the data rate to a value acceptable by the Post Processor.

The Post Processor
The Post Processor directly follows the Preset filter and this block of the AD7725 is fully programmable. The Post Processor core is a systolic array of simple high performance processors. Data is transmitted serially between these processors and it uses local coefficient and data storage and operates synchronously with the master clock.

These processors are grouped into 36 Multiple Accumulate (MAC) blocks (Figure 2) with each block consisting of three multipliers and one adder (Figure 3). Each block can process 3 filter taps and thus the Post Processor allows up to 36x3 = 108 filter taps.

Post Processor Layout

Figure 2. Post Processor Layout

MAC Block

Figure 3. MAC Block

In a systolic array, numerical data is pumped around processors. Each of these processors is allocated to a dedicated function and will only perform that single function. The data is passed between processors and, in this manner, complex operations are performed on the input signal.

The Post Processor core can support any filter structure, whether FIR, IIR, recursive of non-recursive. The core also supports polynomial functions. Data can be transparently decimated or interpolated when passed between processors. This simplifies the design of multi-rate filtering and gives great flexibility when specifying the final output word rate. Following the Preset filter, further, more stringent filtering can be employed in this programmable Post Processor. Either the on-chip default filter response can be loaded into the Post Processor to perform the signal conditioning on the analog input or a user-defined filter response can be loaded. Figure 4 shows a block diagram of the Post Processor.

The Post Processor

Figure 4. The Post Processor

The Post Processor accepts data at CLKIN/8 MHz. Parallel processing is used to split the input data into two data streams- see Figure 5. Each data stream is processed at CLKIN/16 MHz. Parallel processing, therefore, ensures an automatic decimation by two so that the maximum output word rate is CLKIN/16 MHz. Further decimation can be performed is required.

Parallel Processing

Figure 5 Parallel Processing

Post Processor Implementation of an FIR Filter.
The diagrams below show and example of a filtering function implemented on the Post Processor. Figure 6 shows the data path representation of an FIR filter while Figure 7, shows how this algorithm would be implemented on the AD7725. As the Post Processor can implement 3 filter taps per MAC block, 1.3 MAC blocks are required to implement a 4-tap FIR filter. This is a useful guideline when calculating the design requirements for a new application.

4-Tap FIR Filter

Figure 6 4-Tap FIR Filter

4-Tap FIR Filter Post Processor Mapping

Figure 7 4-Tap FIR Filter Post Processor Mapping

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