The AD9650 is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/ 105 MSPS analog-to-digital converter (ADC) designed for digitizing high frequency, wide dynamic range signals with input frequencies of up to 300 MHz.
The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers, and shared integrated voltage reference, which eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.
The ADC output data can be routed directly to the two external 16-bit output ports or multiplexed on a single 16-bit bus. These outputs can be set to either 1.8 V CMOS or LVDS.
Flexible power-down options allow significant power savings, when desired.
Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.
The AD9650 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.
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|AD9650: 16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) Data Sheet (Rev A, 11/2011) (pdf, 3037 kB)||Data Sheets|
|AN-1142: Techniques for High Speed ADC PCB Layout (pdf, 392 kB)||Application Notes|
|AN-878: High Speed ADC SPI Control Software (pdf, 585 kB)||Application Notes|
|AN-807: Multicarrier WCDMA Feasibility (pdf, 969 kB)||Application Notes|
AN-808: Multicarrier CDMA2000 Feasibility
(pdf, 1535 kB)
The goal of this application note is to determine the feasibility of implementing a multicarrier CDMA2000 transceiver and what the major subsystem performances must be.
|AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (pdf, 203 kB)||Application Notes|
|AN-877: Interfacing to High Speed ADCs via SPI (pdf, 1594 kB)||Application Notes|
AN-586: LVDS Outputs for High Speed A/D Converters
(pdf, 207 kB)
High Speed ADCs Uses LVDS (Low-Voltage Differential Signaling) to Minimize Performance Limitations In ADC Applications When Providing High Speed Data Output
AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit (pdf, 452,449 bytes)
(pdf, 441 kB)
This application note describes the operation of a general-purpose, microcontroller-based Serial Port Interface (SPI) boot circuit.
|AN-742: Frequency Domain Response of Switched-Capacitor ADCs (pdf, 401 kB)||Application Notes|
|UG-003: Evaluating the AD9650/AD9268/AD9258/AD9251/AD9231/AD9204 Analog-to-Digital Converters (pdf, 2699 kB)||User Guides|
|MS-2210: Designing Power Supplies for High Speed ADC (pdf, 327 kB)||Technical Articles|
Improve The Design Of Your Passive Wideband ADC Front-End Network
As converter technology improves, so does the demand to resolve very high intermediate frequencies (IFs) accurately at high speeds. This poses two challenges: the converter design itself and the front-end design that couples the signal content to the converter. Even if the converter itself is excellent, the front end must be able to preserve the signal quality too.
(Electronic Design, 3/26/2010)
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ADIsimADC is Analog Devices' Analog-to-Digital Behavioral Model that accurately models the typical performance characteristics of many of our High Speed Converters. The model faithfully reproduces the errors associated with both static and dynamic features such as AC linearity, clock jitter, and many other product specific anomalies.
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|AD9650 IBIS Model (ibs)||IBIS Models||IBS|
Recommended Driver Amplifiers for the AD9650Recommended VGA's for the AD9650
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The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.