Circuit Note (3)
- CN-0285: Broadband Low Error Vector Magnitude (EVM) Direct Conversion Transmitter (pdf, 464 kB)
- CN-0311: Broadband, Low Error Vector Magnitude (EVM) Direct Conversion Transmitter Using LO Divide-by-2 Modulator (pdf, 148 kB)
- CN0294: Increasing the Number of Outputs from a Clock Source Using Low Jitter LVPECL Fanout Buffers (pdf, 420 kB)
Technical Articles (4)
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Clock Requirements For Data Converters
(Electronic Design, 2/2005) -
Design A Clock-Distribution Strategy With Confidence
by Demetrios Efstathiou (Electronic Design, April 27, 2006) -
Speedy A/Ds Demand Stable Clocks
by Jeff Keip, Analog Devices, Inc. (EE Times, 3/18/04) -
Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems
... Much of your system's performance depends on jitter specifications, so careful assessment is critical.
by Brad Brannon, Analog Devices (EDN, 12/7/2004)
ADIsim Design/Simulation Tools (3)
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ADIsimCLK Design and Evaluation Software
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design. -
ADIsimPLL™- Version 3.43
ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market. -
ADIsimRF
ADI’s ADIsimRF design tool provides calculations for the most important parameters within the RF signal chain, including cascaded gain, noise figure, IP3, P1dB, and total power consumption.
Data Sheets (2)
Design & Integration Files (1)
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CN0294 Design & Integration Files
(zip, 1142 kB)
- Schematic
- Bill of Materials
- Gerber Files
- PADS Files
- Assembly Drawing
Device Drivers (1)
Documentation (5)
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ADCLK948 Evaluation Tools
- ADCLK948 Schematic, Rev. C (pdf, 34 kB)
- ADCLK948 Gerber Files, Rev. C (zip, 237 kB)
- ADCLK948 Bill of Materials, Rev. C (xls, 24 kB)
- UG-068: Setting Up the Evaluation Board for the ADCLK948 (pdf, 211 kB)
- UG-435: Evaluation Board for the ADF4351 Fractional-N PLL Frequency Synthesizer (pdf, 1043 kB)
- UG-476: PLL Software Installation Guide (pdf, 520 kB)
- UG-521: Evaluating the CN-0285 Wideband Tx Modulator Solution (pdf, 240 kB)
Evaluation Software (1)
- ADF4351 Evaluation Board Software Rev 4.2.8 (zip, 12056 kB)
FAQs/RAQs (108)
- Are outputs short-circuit protected?
- Are the ADI clock parts stand-alone clock sources or do I still have to buy a clock source to drive these parts?
- Are the CMOS drivers on the clock devices complementary?
- Can I get two clock outputs from the AD9540?
- Can I run CMOS outputs at 5V?
- Can I shift the threshold on clocks for single-ended inputs?
- Can I tri-state the AD9510 outputs?
- Can I use different power supply voltages for the PECL output drivers?
- Can I use the 951X clocks to drive a mixer (RF LO)?
- Do different divide ratios cause variations in jitter?
- Do divide ratios change the propagation delay?
- Do VCXOs have better phase noise and jitter performance than VCOs?
- Do you guarantee performance shown in ADIsimCLK?
- Does jitter vary with different clock frequencies? How about phase noise?
- Does the AD9510 support 2.5V PECL?
- Does the fine delay adjust affect the jitter?
- Help! My PLL came unlocked over temperature.
- How can I determine the die temperature of your device?
- How do harmonic spurs in the output spectrum affect jitter (random or deterministic)?
- How do I choose between active and passive filter in PLL loop?
- How do I determine if a VCO is good enough for my purpose?
- How do I feed a single-ended signal into a differential input?
- How do I get two AD951x (with PLL) to synchronize to the same reference input edge?
- How do I know which VCO will work best with the AD9510?
- How do I optimize my PLL loop for the best phase noise and/or jitter?
- How do I synchronize multiple clock devices?
- How do I use a VCO with a supply greater than 5V?
- How do I use the clock part for jitter clean-up?
- How do the PLLs in the AD951x parts compare to other ADI PLLs?
- How do you determine the bandwidth over which phase noise is integrated to obtain jitter?
- How do you specify jitter?
- How does the clock clean-up function of the AD951x parts work?
- How good does my input signal need to be?
- How long does it take for the PLL to lock?
- How much bandwidth is required to process a PECL or LVDS output?
- I am not using the CLK1 input on the AD9510. Can I just leave it floating?
- I changed the coarse phase adjust in the evaluation software, but nothing happened. What's going on?
- I have a clocking scheme which requires several different division ratios simultaneously. I have a frequency plan, but I'm concerned about crosstalk. How much of a problem is this with your clock distribution chips?
- I have an input present at the clock input, but I'm not seeing an output?
- I have pulled SYNCB low, but I still have output from a channel. Why?
- I ran the AD9510 outputs at 1.4 GHz and they seem to work fine. Is there a problem running them at 1.4 GHz?
- I really need >10 clock outputs. Can I use multiple chips together and still guarantee that all output clocks are synchronized to REFIN?
- I sure can't measure jitter with femtosecond resolution on my scope! How do you do it? How much confidence do you have in the jitter figures that you are quoting for these parts?
- I turned off my reference but the Digital Lock Detect (DLD) still says I'm locked.
- I want to use the phase offset feature on the AD9510 dividers to generate two signals 90° out of phase. How accurate is the phase offset?
- I want to use the variable delay adjust, but the jitter is too high. What can I do?
- I'm trying to write to the part in single-byte mode, but I can't write anything. What am I doing wrong?
- I'm working with optical networks - SONET/SDH. Do ADI's clock chips support these applications?
- If I change the level of PECL output, does it affect the jitter?
- If I use only one of the PECL differential outputs and the unused output is terminated in 50Ω, how will this affect the phase noise or jitter of the single-ended output?
- If jitter can be calculated from phase noise measurements, is it possible to calculate phase noise from jitter numbers?
- Is .01 uF sufficient for power supply pin bypass?
- Is it ok for me to connect the same power supply to both the charge pump and distribution power supply pins?
- Is it okay to AC-couple PECL or LVDS outputs?
- Is it possible to impedance match a clock output if it is heavily loaded? (e.g. CL=100pF)
- Is there a way to cause Input/Output rising edges to be synchronous (zero delay) with the AD9510/11?
- Is there an advantage to running a higher VCO frequency than the output frequency?
- Is there any difference between the nature of an oscillator's phase noise and the phase noise from a clock chip?
- Is there any reason to use a transformer on a differential clock output to obtain a "clean" single-ended clock output?
- May I use the AD9540 for spread spectrum clocking?
- My application has pretty tight power consumption requirements. I am very interested in the capabilities of the AD9510, but I don't need every feature. Is it possible to turn off the unused features and save power?
- My applications are RF, not for clocking data converters. Can ADI's 951X ICs be used for RF applications?
- My circuit board has both an analog GND and a digital GND. How should I connect the AD9510 pins labeled GND?
- My loop is not locking. How do I debug this?
- On my board, I can't get the same low jitter numbers that are shown in the datasheet. Am I doing something wrong?
- On the AD9510, how can I make sure that the duty cycle of output clocks stays within 40% to 60% duty cycle window?
- On the AD9510, what is the relationship between clock output jitter and CLK1/CLK2 input slew rate?
- On the AD951x clock ICs, does the phase offset (coarse delay) affect the jitter?
- Should I reference the passive filter to ground? or supply?
- Should I tie my loop filter to ground or PLL supply?
- Should I use the minimum charge pump current settings in order to minimize power?
- Some of the schematics in the AD951x data sheets show an LVPECL termination scheme which is different from the classic termination often seen (50 Ω to Vs - 2V, or the Thevenin equivalent thereof). How does this work, and how did you chose 200 Ω for the resistors? Can I use 100 ohms to improve the slew rate (or jitter)?
- The AD9510 datasheet says to use an external pull-up resistor on the FUNCTION pin. Why do I need this and what range of resistors will work?
- The loop filter was working great until I changed the divide ratio in PLL. What happened?
- The reference input is differential, but my reference is single-ended. Do I need to convert to differential to drive the AD9510?
- Using the "ADC SNR method", what is the equivalent bandwidth for the jitter specification?
- What are some of the advantages/disadvantages of using LVPECL vs. LVDS outputs?
- What are the best clock sources for a distribution-only design?
- What clock frequency comes out of the AD9510 outputs when you first apply power to the device?
- What happens if I run the part in an ambient environment which exceeds 85°C?
- What happens to the AD9510/11 clock outputs if the Reference Input (REFIN) signal goes away?
- What is the best way to terminate LVPECL outputs to get lowest jitter?
- What is the difference between the coarse phase adjust and the fine delay adjust?
- What is the effect of distributing harmonically related clocks (on chip or on board) in terms of jitter?
- What is the fan-out capability of the CMOS, LVDS, and LVPECL outputs?
- What is the fine delay adjust which is available on certain LVDS/CMOS outputs?
- What is the proper termination (value and location) for outputs?
- What PCB layout recommendations do you have for the of the exposed paddle on the bottom side of the LFCSP package?
- What should I do with unused channels on the AD9510?
- What suppliers do you recommend for VCO/VCXOs?
- What's the advantage of a DDS-based clock generator?
- When a jitter number is specified without an associated bandwidth, what bandwidth should be assumed?
- Which provides better performance - a clock source with sinewave output, or one with differential square wave outputs?
- Who do I contact for technical support on ADIsimCLK?
- Why can I not get the same output amplitude or rise and fall times as stated in your datasheet?
- Why can't I use a bandpass filter for my loop filter?
- Why do I see reference spurs?
- Why do I want to run a fast PFD frequency?
- Why do you recommend AC coupling, rather than DC coupling, at the clock inputs?
- Why does the AD9540 require special filtering on its analog output. What are the requirements of this filter?
- Why doesn't the mini-divider support the divide ratio I want?
- Why doesn't the PLL make my reference input and the clock outputs line up?
- Why don't you spec psrr and cmrr in the datasheet?
- Why is my phase noise shape changing when I change the PLL settings?
- Why is the fine delay adjust not available on all the outputs?
- Why should I use differential rather than single-ended?
- Will differential or single-ended inputs/outputs improve my jitter?
- Will the AD9510 work without a reference input signal?
IBIS Models (1)
- ADCLK948 IBIS Model
Software and Tools (2)
- ADF4351 Evaluation Board Software Rev 4.2.8 (zip, 12056 kB)
-
ADIsimCLK Design and Evaluation Software
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
Solutions Bulletins (2)
Tutorials (3)
- MT-008: Converting Oscillator Phase Noise to Time Jitter (pdf, 123 kB)
- MT-031: Grounding Data Converters and Solving the Mystery of (pdf, 144 kB)
- MT-101: Decoupling Techniques (pdf, 954 kB)
User Guides (4)
- UG-068: Setting Up the Evaluation Board for the ADCLK948 (pdf, 211 kB)
- UG-435: Evaluation Board for the ADF4351 Fractional-N PLL Frequency Synthesizer (pdf, 1043 kB)
- UG-476: PLL Software Installation Guide (pdf, 520 kB)
- UG-521: Evaluating the CN-0285 Wideband Tx Modulator Solution (pdf, 240 kB)
Webcasts (1)
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Fundamentals of Frequency Synthesis, Part 2: Direct Digital Synthesis (DDS)
This month we conclude our two-part series on frequency synthesis, with an introduction to Direct Digital Synthesis. We will give a basic review of how a direct digital synthesis system works, touching on the inner workings of the DDS engine at a relatively high level. We will also discuss the tradeoffs between PLL and DDS technology as a base choice for frequency synthesis needs.
Analog Dialogue (2)
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Analog-to-Digital Converter Clock Optimization: A Test Engineering Perspective
(Analog Dialogue, Vol. 42, February 2008) -
Termination of High-Speed Converter Clock Distribution Devices
(The Back Burner, January 2010)
