SUPPLEMENTAL RESOURCES - CN0174: Low Noise, 12 GHz, Microwave Fractional-N Phase-Locked Loop (PLL) Using an Active Loop Filter and RF Prescaler

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ADIsim Design/Simulation Tools (3)
  • ADIsimPLL™- Version 3.43
    ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.
  • ADIsimPower™ Voltage Regulator Design Tool
    This expert design tool produces custom DC-DC converter designs in about a minute. The user enters 5 inputs and chooses to optimize for efficiency, PCB space, cost, or part count. Output is a complete schematic, BOM, efficiency plot, and performance summary. A PDF summary and a blank PCB is offered for each design to facilitate fast prototyping to verify the design.
  • ADIsimRF
    ADI’s ADIsimRF design tool provides calculations for the most important parameters within the RF signal chain, including cascaded gain, noise figure, IP3, P1dB, and total power consumption.
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Webcasts (2)
  • Fundamentals of Frequency Synthesis, Part 1: Phased Locked Loops
    The first of a two-part series on frequency synthesis, with an introduction to Phased Locked Loops. This webcast looks at the need for frequency generation, the techniques from the past present and future, and how to assess the performance of a frequency synthesis, and real world applications. Particular attention will be focused on Phase Locked Loops (PLL's) as frequency synthesizers.
  • Fundamentals of Frequency Synthesis, Part 2: Direct Digital Synthesis (DDS)
    This month we conclude our two-part series on frequency synthesis, with an introduction to Direct Digital Synthesis. We will give a basic review of how a direct digital synthesis system works, touching on the inner workings of the DDS engine at a relatively high level. We will also discuss the tradeoffs between PLL and DDS technology as a base choice for frequency synthesis needs.
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