Application Notes (36)
- AN-1142: Techniques for High Speed ADC PCB Layout (pdf, 392 kB)
- AN-0974: Multicarrier TD-SCMA Feasibility (pdf, 634 kB)
- AN-953: Direct Digital Synthesis (DDS) with a Programmable Modulus (pdf, 112 kB)
- AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (pdf, 221 kB)
- AN-935: Designing an ADC Transformer-Coupled Front End (pdf, 363 kB)
- AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (pdf, 170 kB)
- AN-905: VisualAnalog Converter Evaluation Tool Version 1.0 User Manual (pdf, 2124 kB)
- AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (pdf, 207 kB)
- AN-851: A WiMax Double Downconversion IF Sampling Receiver Design (pdf, 262 kB)
- AN-847: Measuring a Grounded Impedance Profile Using the AD5933 (pdf, 294 kB)
- AN-843: Measuring a Loudspeaker Impedance Profile Using the AD5933 (Rev. A, 6/07) (pdf, 284 kB)
- AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (pdf, 313 kB)
- AN-835: Understanding High Speed ADC Testing and Evaluation (pdf, 985 kB)
-
AN-823: Direct Digital Synthesizers in Clocking Applications Time
(pdf, 115 kB)
Jitter in Direct Digital Synthesizer-Based Clocking Systems -
AN-808: Multicarrier CDMA2000 Feasibility
(pdf, 1535 kB)
The goal of this application note is to determine the feasibility of implementing a multicarrier CDMA2000 transceiver and what the major subsystem performances must be. - AN-807: Multicarrier WCDMA Feasibility (pdf, 969 kB)
- AN-772: A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP) (pdf, 439 kB)
- AN-769: Generating Multiple Clock Outputs from the AD9540 (pdf, 0)
- AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (pdf, 291 kB)
- AN-737: How ADIsimADC Models an ADC (pdf, 373 kB)
- AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated (pdf, 370 kB)
- AN-632: Provisionary Data Rates Using the AD9951 DDS as an Agile Reference Clock for the ADN2812 Continuous-Rate CDR (pdf, 138 kB)
-
AN-621: Programming the AD9832/AD9835
(pdf, 202 kB)
This application note details how to program 5 MHz on the output of the AD9832/AD9835 parts. The frequency register,defer register,and command sequence are explained in detail. - AN-605: Synchronizing Multiple AD9852 DDS-Based Synthesizers (pdf, 527 kB)
- AN-587: Synchronizing Multiple AD9850/AD9851 DDS-Based Synthesizers (pdf, 116 kB)
-
AN-586: LVDS Outputs for High Speed A/D Converters
(pdf, 207 kB)
High Speed ADCs Uses LVDS (Low-Voltage Differential Signaling) to Minimize Performance Limitations In ADC Applications When Providing High Speed Data Output -
AN-557: An Experimenter's Project:
(pdf, 368 kB)
Incorporating the AD9850 Complete DDS Device as a Digital LO Function in an Amateur Radio Transceiver -
AN-543: High Quality, All-Digital RF Frequency Modulation Generation with the ADSP-2181 and the AD9850 DDS
(pdf, 49 kB)
- AN-543 - Monaural FM Transmitter (dsp, 20 kB)
- AN-543 - Stereo FM Transmitter (dsp, 25 kB)
-
AN-501: Aperture Uncertainty and ADC System Performance
(pdf, 227 kB)
A Key Concern in IF Sampling is that of Aperture Uncertainty (Jitter) - AN-423: Amplitude Modulation of the AD9850 Direct Digital Synthesizer (pdf, 37 kB)
- AN-419: A Discrete, Low Phase Noise, 125 MHz Crystal Oscillator for the AD9850 (pdf, 101 kB)
-
AN-345: Grounding for Low-and-High-Frequency Circuits
(pdf, 455 kB)
Know Your Ground and Signal Paths for Effective Designs. Current Flow Seeks Path of Least Impedance-Not Just Resistance.... -
AN-342: Analog Signal-Handling for High Speed and Accuracy.
(pdf, 468 kB)
Signal handling techniques for optimizing DAC and ADC performance. - AN-282: Fundamentals of Sampled Data Systems (pdf, 2131 kB)
-
AN-280: Mixed Signal Circuit Technologies
(pdf, 2101 kB)
Considers problems which arise when reality (& Murphy) intervene in a design which otherwise seems satisfactory in terms of theory and modeling. - AN-237: Choosing DACs for Direct Digital Synthesis (pdf, 1156 kB)
Circuit Note (3)
- CN-0109: Low Jitter Sampling Clock Generator for High Performance ADCs Using the AD9958/AD9858 500 MSPS/1GSPS DDS and AD9515 Clock Distribution IC (pdf, 114 kB)
- CN-0121: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (pdf, 384 kB)
- CN-0186: Phase Coherent FSK Modulator (pdf, 239 kB)
Technical Articles (37)
-
400-MSample DDSs Run On Only +1.8 VDC
... This line of highly integrated DDS ICs features on-board RAM and crystal-oscillator circuitry to simplify the generation of agile and exotic waveforms. (Microwaves & RF Cover Story, 12/2002) -
AD9858: Flexible Integrated Synthesizer For Wireless
... The most important feature of the AD9858 is its ability to change frequency in less than 5 ns, meaning that there is virtually no application left where you will need to go the expense of switching between two separate synthesizers. (AnalogZone, RF/IF Zone Products for the Week of 9/23/2002) -
ADI Buys Korean Mobile TV Chip Maker
(EE Times, 6/7/2006) - Basics of Designing a Digital Radio Receiver (Radio 101) (pdf, 77 kB)
-
Bridging The Analog/ Digital Domain
by Cheryl Ajluni
(Wireless Systems Design, September 2001) -
Buffer Adapts Single-ended Signals for Differential Inputs
by Randall Carver, Analog Devices (EDN Design Idea, 9/2/2004) -
Clock Requirements For Data Converters
(Electronic Design, 2/2005) -
Converters for 3G are Optimized for Cost, Size and Power
by Chris Cloninger, Analog Devices, Inc. (Planet Analog, 4/6/2006) -
Correlating High-Speed ADC Performance to Multicarrier 3G Requirements
by Brad Brannon (RF Design, 6/1/2003) -
DDS Applications
by Eva Murphy and Colm Slattery, Analog Devices, Inc. (EETimes, 9/26/2005) -
DDS Circuit Generates Precise PWM Waveforms
by Colm Slattery, Analog Devices, Inc. (EDN, 10/2/2003) -
DDS Design
By David Brandon, Analog Devices, Inc.
Direct digital synthesizers are known for their highly accurate digital tuning, low noise figure, and phase-continuous frequency-hopping capabilities, which make them more attractive than alternative analog frequency-synthesis solutions.
(EDN, 5/13/2004) -
DDS Device Produces Sawtooth Waveform
Ramp or sawtooth waveforms are useful for a broad range of applications, including automatic-test equipment, benchtest equipment, and actuator control. (EDN Design Idea, 7/10/2003) -
DDS Device Provides Amplitude Modulation
by Mary McCarthy, Analog Devices, Inc.
(EDN, September 2, 1999) -
DDS IC Initiates Synchronized Signals
(Microwaves & RF Cover Story, July 2005) -
DDS IC Plus Frequency-To-Voltage Converter Make Low-Cost DAC
by Noel McNamara, Analog Devices, Inc. (EDN Design Idea, 2/5/2004) -
DDS Simplifies Polar Modulation
By Ken Gentile, Analog Devices ... Basic modulation mathematics and DDS (direct digital synthesis) provide designers with an all-digital technique for generating polar-encoded carrier signals. (EDN, 8/5/2004) -
DDS Tackles BaseStations Head On
... This High-Performance, Low-Power Integrated Hybrid Synthesizer Flaunts A 10-b Digital-To-Analog Converter That Operates At Up To 1 GSample/s.
(Wireless Systems Design, September 2002) -
Design A Clock-Distribution Strategy With Confidence
by Demetrios Efstathiou (Electronic Design, April 27, 2006) -
Digital Potentiometers Vary Amplitude In DDS Devices
(Electronic Design, Ideas for Design, 5/29/2000) - Digital Up/Down Converters: VersaCOMM™ White Paper (pdf, 97 kB)
-
Digital Waveform Generator Provides Flexible Frequency Tuning for Sensor Measurement
by Colm Slattery, Analog Devices (EDN, 12/17/2004) -
DNL and Some of its Effects on Converter Performance
... by Brad Brannon, Analog Devices, Inc. (Wireless Design & Development, June 2001) -
Healthcare at Home (Part II)
A major trend in medicine is to move treatments and monitoring out of the hospital or even the doctor's office and either attach them to the patient or enable it to be done in the home. What can device designers do to aid this effort and what technologies would help to enable it.
(EDN, February 25, 2008) -
Improved DDS Devices Enable Advanced Comm Systems
by Valoree Young, Analog Devices
(Electronic Products, September 2006) -
Integrated DDS Chip Takes Steps To 2.7 GHz
This highly integrated 2.7-GHz source includes all essential DDS circuitry along with a clock driver, divider, high-resolution DAC, and combination phase detector/charge pump. (ED Online, April 2004) -
Introducing Digital Up/Down Converters: VersaCOMM™ Reconfigurable Digital Converters
(pdf, 63 kB)
Revolutionize your radio architectures - Low-power direct digital synthesizer cores enable high level of integration
- MS-2210: Designing Power Supplies for High Speed ADC (pdf, 327 kB)
-
Proper Grounding Is Critical For High-Speed Systems
... by Walt Kester and James Bryant, Analog Devices, Inc. (Wireless Systems Design, May 2000) -
Simple Circuit Controls Stepper Motors
by Noel McNamara, Analog Devices, Inc. (EDN Design Idea, 1/8/04) -
Speedy A/Ds Demand Stable Clocks
by Jeff Keip, Analog Devices, Inc. (EE Times, 3/18/04) -
Synchronized Synthesizers Aid Multichannel Systems
by David Brandon and John Kornblum, Analog Devices, Inc. (Microwaves & RF, 9/2005) -
The Year of the Waveform Generator
(Test & Measurement World, 12/1/2005) -
Two DDS ICs Implement Amplitude-shift Keying
by Noel McNamara, Analog Devices, Inc. (EDN Design Idea, 12/25/2003) -
Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems
... Much of your system's performance depends on jitter specifications, so careful assessment is critical.
by Brad Brannon, Analog Devices (EDN, 12/7/2004) -
Video Portables and Cameras Get HDMI Outputs
By Doug Bartow, Analog Devices, Inc.
ADIsim Design/Simulation Tools (3)
-
ADIsimADC
ADIsimADC is Analog Devices' Analog-to-Digital Behavioral Model that accurately models the typical performance characteristics of many of our High Speed Converters. The model faithfully reproduces the errors associated with both static and dynamic features such as AC linearity, clock jitter, and many other product specific anomalies. -
ADIsimCLK Design and Evaluation Software
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design. -
ADIsimDDS™
The purpose of this tool is to assist a user in selecting and evaluating Analog Devices, Direct Digital Synthesis (DDS) IC's. It allows a user to select a device, enter the desired operating conditions and evaluate it's general performance.
Aerospace Information (3)
-
Aerospace Dice
(pdf, 196 kB)
(Revised 1/2006)
Many Analog Devices products can be purchased as Class K die. -
PCN#00-406
(pdf, 14 kB)
(4/14/00)
Product Change notice for change of Analog Devices, Inc. Aerospace Product Line standard product from 883 Class S to MIL-PRF-38535, level V. -
Standard Space Level Products Program
(pdf, 39 kB)
This brochure describes the standard flow and how to order Analog Devices, Inc. standard product for Space Level not available as JAN, or QML. It replaces the Standard Class S brochure.
Cross Reference Guides (3)
-
Military Part Cross-Reference Guide
(pdf, 29 kB)
This cross-reference lists the recommended Analog Devices military grade replacements for products manufactured by AMD, Burr-Brown, Elantec, Motorola, and Philips. Products covered include 'direct replacement' products from Analog Devices and those with minor specification differences. Also listed is the complete manufacturer's model number and generic function/description. - Military Products by Function (pdf, 7 kB)
-
Military Products by GENERIC Part Number
(pdf, 16 kB)
For Class S, QML Level V, and radiation guaranteed products go to the Aerospace Products page.
Data Sheets (13)
- AD6645: 14-Bit, 80 MSPS/105 MSPS A/D Converter Data Sheet (Rev D, 10/2008) (pdf, 842 kB)
- AD9512: 1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs Data Sheet (Rev A, 06/2005) (pdf, 960 kB)
- AD9513: 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs Data Sheet (Rev 0, 09/2005) (pdf, 603 kB)
- AD9514: 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Output Data Sheet (Rev 0, 08/2005) (pdf, 627 kB)
- AD9515: 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs Data Sheet (Rev A, 04/2012) (pdf, 650 kB)
- AD9858: 1 GSPS Direct Digital Synthesizer Data Sheet (Rev C, 02/2009) (pdf, 919 kB)
- AD9910: 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer Datasheet (Rev D, 05/2012) (pdf, 839 kB)
- AD9911: 500 MSPS Direct Digital Synthesizer with 10-Bit DAC Data Sheet (Rev 0, 05/2006) (pdf, 937 kB)
- AD9912: 1 GSPS Direct Digital Synthesizer with 14-Bit DAC Data Sheet (Rev F, 06/2010) (pdf, 926 kB)
- AD9913: Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer Data Sheet (Rev A, 06/2010) (pdf, 683 kB)
- AD9954: 400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer Data Sheet (Rev B, 05/2009) (pdf, 780 kB)
- AD9958: 2-Channel 500 MSPS DDS with 10-Bit DACs Data Sheet (Rev B, 04/2013) (pdf, 1051 kB)
- AD9959: 4 Channel 500 MSPS DDS with 10-Bit DACs Data Sheet (Rev B, 07/2008) (pdf, 866 kB)
Design Handbooks (3)
-
A Technical Tutorial on Digital Signal Synthesis
(pdf, 901 kB)
Copyright © 1999 Analog Devices, Inc. -
High Speed System Applications
- Table of Contents (pdf, 2296 kB)
- Section 1: High Speed Data Conversion Overview (pdf)
- Section 2: Optimizing Data Converter Interfaces (pdf, 1677 kB)
- Section 3: DAC, DDS, PLL's, and Clock Distribution (pdf, 7676 kB)
- Section 4: PC Board Layout and Design Tools (pdf, 3570 kB)
- The Data Conversion Handbook
Documentation (23)
-
AD6644 and AD6645 Evaluation Tools
Details on the evaluation board can be found in the back of the data sheet for this product. The data sheet can be accessed through the product page.- AD6644/AD6645 Evaluation Board Bill of Materials (pdf, 16 kB)
- AD6644/AD6645 Evaluation Board Schematics (pdf, 54 kB)
- AD6644/AD6645 Evaluation Board Gerber Files (zip, 638 kB)
- AD9511/AD9512 All Layers, Rev. B (pdf, 239 kB)
- AD9511/AD9512 Gerber Files, Rev. B (zip, 206 kB)
- AD9511/AD9512 Schematics, Rev. B (pdf, 323 kB)
- AD9512 Evaluation Tools
-
AD9513/AD9514/AD9515 Evaluation Tools
- AD9513/AD9514/AD9515 Evaluation Board, Rev. 0 (pdf, 306 kB)
- AD9513/AD9514/AD9515 Evaluation Board Schematic, Rev. B (pdf, 165 kB)
- AD9513 Evaluation Board Bill of Materials, Rev. B (Pb-Free) (xls, 34 kB)
- AD9514 Evaluation Board Bill of Materials, Rev. B (Pb-Free) (xls, 35 kB)
- AD9515 Evaluation Board Bill of Materials, Rev. B (Pb-Free) (xls, 35 kB)
- AD9513/AD9514/AD9515 Gerber Files, Rev. B (zip, 78 kB)
-
AD9858 Evaluation Software
-
Evaluation Board Software Installer for Win 9x,Me,NT4 SP3, 2000, XP Operating Systems (Rev 1.2)
(exe, 6,768,001 bytes) -
AD9858 Evaluation Software Source Code (Rev 1.2.1)
(exe, 215,175 bytes)
-
Evaluation Board Software Installer for Win 9x,Me,NT4 SP3, 2000, XP Operating Systems (Rev 1.2)
-
AD9858 Fractional Divider Evaluation Board Tools
- Documentation (pdf, 294 kB)
- Schematics (pdf, 304 kB)
- Bill of Materials (Pb-Free) (xls, 27 kB)
- Gerber Files (zip, 231 kB)
-
AD9858 Generic DDS DAC Output Evaluation Board Tools
- Documentation (pdf, 266 kB)
- Schematics (pdf, 345 kB)
- Bill of Materials (Pb-Free) (xls, 28 kB)
- Gerber Files (zip, 523 kB)
-
AD9858 Translation Loop Evaluation Board Tools
- Documentation (pdf, 275 kB)
- Schematics (pdf, 333 kB)
- Bill of Materials (Pb-Free) (xls, 29 kB)
- Gerber Files (zip, 230 kB)
-
AD9859, AD9951, AD9952, AD9953 and AD9954 Evaluation Tools
- AD9859, AD9951-AD9954 Evaluation Software Installer for Windows 95,98 and Me
- AD9859, AD9951-AD9954 Evaluation Software Installer for Windows NT4
- AD9859, AD9951-AD9954 Evaluation Software Installer for Windows 2000 and Xp
- AD9859, AD9951-AD9954 Evaluation Software Source Code, Rev 1.8 (zip, 307 kB)
- AD9859, AD9951-AD9954 Evaluation Board Gerber Files, Rev. D (zip, 409 kB)
-
AD9859, AD9951, AD9952, AD9953 and AD9954 Evaluation Board Schematics, Rev. D
(pdf, 430 kB)
The AD9859, AD9951, AD9952, AD9953 and AD9954 all use the same Evaluation Board. - AD9859 Evaluation Board Bill of Materials, Rev. D (Pb-Free) (xls, 30 kB)
- AD9951 Evaluation Board Bill of Materials, Rev. D (Pb-Free) (xls, 30 kB)
- AD9952 Evaluation Board Bill of Materials, Rev. D (Pb-Free) (xls, 33 kB)
- AD9953 Evaluation Board Bill of Materials, Rev. D (Pb-Free) (xls, 30 kB)
- AD9954 Evaluation Board Bill of Materials, Rev. D (Pb-Free) (xls)
-
AD9910 Evaluation Tools
- AD9910/PCBZ Data Sheet (pdf, 1297 kB)
- Bill of Materials, Rev. G (xls, 72 kB)
- Evaluation Software, Rev. 1.0.1 (zip)
- Evaluation Source Code, Rev. 1.0.0 (zip)
- Evaluation Board Schematics, Rev. G (pdf)
- Gerber Files, Rev. G (zip, 257 kB)
- AD9911 Evaluation Board Documentation for 500 MSPS DDS with 10-Bit DAC (pdf, 1006 kB)
-
AD9911 Evaluation Tools
-
AD9911 Evaluation Software, Version 0.0.6
(Runs on Windows 98, Me, 2000, or XP) - AD9911 Schematics, Rev. A (pdf, 298 kB)
- AD9911 Evaluation Board Pb-Free Bill of Materials, Rev. A (pdf, 14 kB)
- AD9911 Evaluation Board Gerber Files, Rev. A (zip, 203 kB)
- AD9911 Evaluation Source Code (zip, 243 kB)
-
AD9911 Evaluation Software, Version 0.0.6
-
AD9912 Evaluation Tools
- AD9912 Schematic, Rev. B (pdf)
- AD9912 Schematic, Rev. A (pdf, 399 kB)
- AD9912 Gerber Files, Rev. B (zip)
- AD9912 Gerber Files, Rev. A (zip, 268 kB)
- AD9912 Evaluation Software, Rev. 1.02 (zip, 5878 kB)
- AD9912/PCBZ Evaluation Board RoHS Bill of Materials (Rev B) (xls)
- AD9912 Evaluation Board Data Sheet, Rev. 0 (pdf, 558 kB)
-
AD9913 Evaluation Board/Tools
- Evaluation Board, Rev. 0 (pdf, 751 kB)
- Evaluation Software, (Rev. 0.0.9) (zip, 6109 kB)
- Software Source Code (Rev. 0.0.9) (zip)
- Evaluation Board Schematics, Rev. C (pdf, 105 kB)
- Evaluation Board BOM, Rev. C (xls, 78 kB)
- Evaluation Board Gerber Files, Rev. C (zip, 191 kB)
-
AD9958 and AD9959 Evaluation Tools
- AD9958/AD9959 Schematics, Rev. C (pdf, 461 kB)
- AD9958/AD9959 Evaluation Board Gerber Files, Rev. C (zip, 825 kB)
-
AD9958/AD9959 Evaluation Software, Rev 1.0
(zip, 5830 kB)
Runs on Windows 98, Me, 2000, or XP. - AD9958/AD9959 Evaluation Software Source Code (Rev 0.0.8) (zip, 233 kB)
- AD9958 Evaluation Board Bill of Materials, Rev. C (Pb-Free) (xls, 35 kB)
- AD9959 Evaluation Board Bill of Materials, Rev. C (Pb-Free) (xls, 37 kB)
- AD9958 Evaluation Board Data Sheet (pdf, 4304 kB)
-
AD9959 Evaluation Board Data Sheet
(pdf, 1530 kB)
Evaluation Board for 4-Channel 500 MSPS DDS with 10-Bit DACs. This document serves as a guide to the setup and use of the AD9959 Evaluation Board. -
ADIsimADC
ADIsimADC is Analog Devices' Analog-to-Digital Behavioral Model that accurately models the typical performance characteristics of many of our High Speed Converters. The model faithfully reproduces the errors associated with both static and dynamic features such as AC linearity, clock jitter, and many other product specific anomalies. - PLL Loop Filter Tool (xls, 5336 kB)
- UG-173: High Speed ADC USB FIFO Evaluation Kit (HSC-ADC-EVALB-DCZ) (pdf, 774 kB)
-
UG-207: Evaluation Board User Guide for AD9910
(pdf, 956 kB)
Evaluation Board for 1 GSPS DDS with 14-Bit DAC
FAQs/RAQs (152)
- Are any of your DDS products space qualified?
- Are frequency changes of a DDS phase coherent?
- Are outputs short-circuit protected?
- Are the ADI clock parts stand-alone clock sources or do I still have to buy a clock source to drive these parts?
- Are the CMOS drivers on the clock devices complementary?
- Are there any specific recommendations for material in the vias of the circuit board for the thermally enhanced package styles in which some ADI DDS' are available?
- Can I gate the REF CLK on and off?
- Can I get two clock outputs from the AD9540?
- Can I read back data at the same rate that I can write the data to the DDS device?
- Can I run CMOS outputs at 5V?
- Can I shift the threshold on clocks for single-ended inputs?
- Can I tri-state the AD9510 outputs?
- Can I use different power supply voltages for the PECL output drivers?
- Can I use the 951X clocks to drive a mixer (RF LO)?
- Can I use the same power supply for AVDD and DVDD?
- Can the DDS evaluation boards be integrated directly into a system project?
- Do different divide ratios cause variations in jitter?
- Do divide ratios change the propagation delay?
- Do VCXOs have better phase noise and jitter performance than VCOs?
- Do you guarantee performance shown in ADIsimCLK?
- Do you have a DDS overview?
- Do you recommend a linear or switching power supply?
- Does Analog Devices offer a list of manufacturers of oscillators for DDS devices?
- Does jitter vary with different clock frequencies? How about phase noise?
- Does the AD9510 support 2.5V PECL?
- Does the fine delay adjust affect the jitter?
- Help! My PLL came unlocked over temperature.
- How can I control the envelope of the output?
- How can I determine the die temperature of your device?
- How can I synchronize multiple DDS parts?
- How do harmonic spurs in the output spectrum affect jitter (random or deterministic)?
- How do I change the phase of my output signal?
- How do I choose between active and passive filter in PLL loop?
- How do I determine if a VCO is good enough for my purpose?
- How do I feed a single-ended signal into a differential input?
- How do I get two AD951x (with PLL) to synchronize to the same reference input edge?
- How do I know which VCO will work best with the AD9510?
- How do I optimize my PLL loop for the best phase noise and/or jitter?
- How do I perform amplitude modulation on the output?
- How do I synchronize multiple clock devices?
- How do I use a DDS for a clock driver?
- How do I use a VCO with a supply greater than 5V?
- How do I use the clock part for jitter clean-up?
- How do the PLLs in the AD951x parts compare to other ADI PLLs?
- How do you determine the bandwidth over which phase noise is integrated to obtain jitter?
- How do you specify jitter?
- How does the clock clean-up function of the AD951x parts work?
- How good does my input signal need to be?
- How long does it take for the PLL to lock?
- How much bandwidth is required to process a PECL or LVDS output?
- I am having problems getting my evaluation software to see my evaluation board; what should I do to correct the problem?
- I am not using the CLK1 input on the AD9510. Can I just leave it floating?
- I changed the coarse phase adjust in the evaluation software, but nothing happened. What's going on?
- I have a clocking scheme which requires several different division ratios simultaneously. I have a frequency plan, but I'm concerned about crosstalk. How much of a problem is this with your clock distribution chips?
- I have an input present at the clock input, but I'm not seeing an output?
- I have limited experience working with thermally enhanced packages. Where can I get information concerning the proper techniques for soldering and assembly?
- I have limited power to supply to the part. What can I do to reduce the power consumption of the device and thus ensure that my supply is adequate?
- I have pulled SYNCB low, but I still have output from a channel. Why?
- I need to operate my DDS part above the rated temperature range. Can you give me any reliability data?
- I ran the AD9510 outputs at 1.4 GHz and they seem to work fine. Is there a problem running them at 1.4 GHz?
- I really need >10 clock outputs. Can I use multiple chips together and still guarantee that all output clocks are synchronized to REFIN?
- I sure can't measure jitter with femtosecond resolution on my scope! How do you do it? How much confidence do you have in the jitter figures that you are quoting for these parts?
- I turned off my reference but the Digital Lock Detect (DLD) still says I'm locked.
- I want to use the phase offset feature on the AD9510 dividers to generate two signals 90° out of phase. How accurate is the phase offset?
- I want to use the variable delay adjust, but the jitter is too high. What can I do?
- I would like to update the FTW of my DDS, but only a single byte of the FTW needs to change. Can the frequency tuning word of a DDS be partially updated a byte at a time?
- I'm not using all the blocks of the AD9858. What do I do with the unused inputs of these sections?
- I'm trying to write to the part in single-byte mode, but I can't write anything. What am I doing wrong?
- I'm working with optical networks - SONET/SDH. Do ADI's clock chips support these applications?
- If I change the level of PECL output, does it affect the jitter?
- If I use only one of the PECL differential outputs and the unused output is terminated in 50Ω, how will this affect the phase noise or jitter of the single-ended output?
- If I violate the proper logic level of the REF CLK (that is, underdrive or overdrive it), what can I expect?
- If jitter can be calculated from phase noise measurements, is it possible to calculate phase noise from jitter numbers?
- If the port has a differential REF CLK, and I want to use a single-ended clock, what do I do with the other differential input?
- Is .01 uF sufficient for power supply pin bypass?
- Is all DDS software supplied by Analog Devices compatible with all WinXX versions?
- Is it ok for me to connect the same power supply to both the charge pump and distribution power supply pins?
- Is it okay to AC-couple PECL or LVDS outputs?
- Is it possible to impedance match a clock output if it is heavily loaded? (e.g. CL=100pF)
- Is there a way to cause Input/Output rising edges to be synchronous (zero delay) with the AD9510/11?
- Is there an advantage to running a higher VCO frequency than the output frequency?
- Is there any difference between the nature of an oscillator's phase noise and the phase noise from a clock chip?
- Is there any reason to use a transformer on a differential clock output to obtain a "clean" single-ended clock output?
- May I use the AD9540 for spread spectrum clocking?
- My application has pretty tight power consumption requirements. I am very interested in the capabilities of the AD9510, but I don't need every feature. Is it possible to turn off the unused features and save power?
- My applications are RF, not for clocking data converters. Can ADI's 951X ICs be used for RF applications?
- My circuit board has both an analog GND and a digital GND. How should I connect the AD9510 pins labeled GND?
- My evaluation board is not working; the software is reporting a USB Communication Error. I verified that the evaluation board is connected to the PC and powered. What else can I check?
- My loop is not locking. How do I debug this?
- On my board, I can't get the same low jitter numbers that are shown in the datasheet. Am I doing something wrong?
- On the AD9510, how can I make sure that the duty cycle of output clocks stays within 40% to 60% duty cycle window?
- On the AD9510, what is the relationship between clock output jitter and CLK1/CLK2 input slew rate?
- On the AD951x clock ICs, does the phase offset (coarse delay) affect the jitter?
- Should I reference the passive filter to ground? or supply?
- Should I separate digital and analog ground planes on my evaluation board?
- Should I tie my loop filter to ground or PLL supply?
- Should I use the minimum charge pump current settings in order to minimize power?
- Some of the schematics in the AD951x data sheets show an LVPECL termination scheme which is different from the classic termination often seen (50 Ω to Vs - 2V, or the Thevenin equivalent thereof). How does this work, and how did you chose 200 Ω for the resistors? Can I use 100 ohms to improve the slew rate (or jitter)?
- The AD9510 datasheet says to use an external pull-up resistor on the FUNCTION pin. Why do I need this and what range of resistors will work?
- The loop filter was working great until I changed the divide ratio in PLL. What happened?
- The reference input is differential, but my reference is single-ended. Do I need to convert to differential to drive the AD9510?
- Using the "ADC SNR method", what is the equivalent bandwidth for the jitter specification?
- What are some of the advantages/disadvantages of using LVPECL vs. LVDS outputs?
- What are the advantages and disadvantages of serial and parallel mode?
- What are the best clock sources for a distribution-only design?
- What are the proper logic input levels for the DDS parts?
- What causes a Quadrature Digital Upconverter (AD9856, AD9857) to go into a CIC overflow condition?
- What clock frequency comes out of the AD9510 outputs when you first apply power to the device?
- What happens if I run the part in an ambient environment which exceeds 85°C?
- What happens to the AD9510/11 clock outputs if the Reference Input (REFIN) signal goes away?
- What is the best way to terminate LVPECL outputs to get lowest jitter?
- What is the difference between the coarse phase adjust and the fine delay adjust?
- What is the effect of distributing harmonically related clocks (on chip or on board) in terms of jitter?
- What is the effect of increasing my supply voltage beyond the nominal recommended value?
- What is the effect of REF CLK jitter on the DDS?
- What is the fan-out capability of the CMOS, LVDS, and LVPECL outputs?
- What is the fine delay adjust which is available on certain LVDS/CMOS outputs?
- What is the maximum speed I can write to the part?
- What is the proper termination (value and location) for outputs?
- What is the proper termination for the DAC outputs for the DDS products?
- What is the ratio between the analog and digital currents drawn by the DDS devices?
- What kind of problems can I expect from exceeding the maximum clock rate? (power dissipation, spectral problems)
- What layout recommendations do you have for the power supply pins of the DDS device?
- What logic families can interface with our parts?
- What PCB layout recommendations do you have for the of the exposed paddle on the bottom side of the LFCSP package?
- What should I do with unused channels on the AD9510?
- What suppliers do you recommend for VCO/VCXOs?
- What type of automatic frequency sweeping modes does each of your DDS parts support?
- What type of frequency sweeping is available?
- What type of signal source is recommended?
- What's the advantage of a DDS-based clock generator?
- When a jitter number is specified without an associated bandwidth, what bandwidth should be assumed?
- Where can I find some good background material on direct digital synthesis?
- Which provides better performance - a clock source with sinewave output, or one with differential square wave outputs?
- Who do I contact for technical support on ADIsimCLK?
- Why can I not get the same output amplitude or rise and fall times as stated in your datasheet?
- Why can't I see a signal at the output of my DDS when it is unterminated? (I'm setting everything correctly, but I'm just probing the output pins of the DDS which have nothing connected to them.)
- Why can't I use a bandpass filter for my loop filter?
- Why did the model numbers change on the AD9852 and AD9854 products? I thought they were available in the ASQ package.
- Why do I see reference spurs?
- Why do I want to run a fast PFD frequency?
- Why do you recommend AC coupling, rather than DC coupling, at the clock inputs?
- Why does spectral performance degrade when using larger values of multiplication on the clock multiplier?
- Why does the AD9540 require special filtering on its analog output. What are the requirements of this filter?
- Why doesn't the mini-divider support the divide ratio I want?
- Why doesn't the PLL make my reference input and the clock outputs line up?
- Why don't you spec psrr and cmrr in the datasheet?
- Why is my phase noise shape changing when I change the PLL settings?
- Why is the fine delay adjust not available on all the outputs?
- Why should I use differential rather than single-ended?
- Will differential or single-ended inputs/outputs improve my jitter?
- Will the AD9510 work without a reference input signal?
IBIS Models (11)
- AD6645 IBIS Models
- AD9512 IBIS Models
- AD9513 IBIS Models
- AD9514 IBIS Models
- AD9515 IBIS Models
- AD9858 IBIS Model
- AD9910 IBIS Model
- AD9912 IBIS Models
- AD9913 IBIS Model
- AD9954 IBIS Models
- AD9959 IBIS Models
Overview (7)
-
AD9858 DDS Performance Improvements
(pdf, 440 kB)
Recent efforts have yielded significant improvement to the achievable performance of the AD9858. - Clock and Timing ICs (pdf, 4970 kB)
- Direct Digital Synthesis (DDS) Featured Products
- Expanding Family of Integrated Clock ICs
- Leading Inside Advertorials: Single-Chip Clock Generator with 14-Channel Distribution Solves Timing Challenges in Networks (pdf, 64 kB)
-
Reset your thinking about clocks.
(pdf, 153 kB)
... In precision timing, analog is everywhere. -
RF Source Booklet
(pdf, 815 kB)
RF IC Product Overview - Version O (11/2012)
Packages Application Notes (1)
Product Reviews (21)
-
Analog - Industy's Fastest Digital Synthesizers Integrate 14-Bit DACs
(Electropages, 1/15/2007) -
Analog Devices Expands Radio Frequency IC Offerings with New Family Of Direct Digital Synthesizers
... New DDS family delivers high clock speed with record low power dissipation (ChipCenter, Analog Avenue Product of the Week) -
Analog Devices Introduces Two New Multichannel DDS Devices
(Wireless Design Online, 7/22/2005) -
Analog Devices Rolls Out Multi-channel DDS Devices
(EETimes, 7/22/3005) -
Circuit Simulation Tool Simplifies Clock Designs
(eeProductCenter, 8/23/2005) -
Clock-circuit-design Tool Recovers Engineer Time
(EDN, 8/23/2005) -
DDS IC Initiates Synchronized Signals
(Microwaves and RF, 7/2005) -
Digital Synthesizers House 14-b DACs
(Microwaves & RF, 1/2007) -
Direct Digital Synthesizer with Spur-Reduction Channels Offers Improved Dynamic Range
(eeProductCenter, 6/4/2007) -
Direct Digital Synthesizers Cut Power by 90 Percent
(CommsDesign, an EE Times Community, 1/6/2003) -
eeProductCenter Ultimate Products
AD9959/AD9958 selected by EE Times Editors as one of the 10 most significant products covered on eeProductCenter in the quarter (3Q05). (eeProductCenter, 1/2006) -
Free Direct Digital Synthesis IC Evaluation Tool
(Control Engineering, 9/14/2006) -
Independently Programmable DDS Boasts Multichannel Capability
(RFDesign, 7/21/2005) -
Multichannel DDS Chips Aim to Smooth Synchronization Snafus
(EDN, 7/21/2005) -
On-Line Evaluation Tool Simplifies Implementing DDS Semiconductors
(eeProductCenter, 8/16/2006) -
Specialized Data Converters Move Up The Signal Chain
(Electronic Design, 1/11/2007) -
Synthesizer ICs with On-Chip 14-Bit DACs Tout 1 GSPS Operation
(eeProductCenter, 12/5/2006) -
Top Products of 2005
Microwave & RF names the AD9959 and AD9958 to its Top Products list (Microwave & RF, 12/2005) -
Tuning Gets Easier With Industry's First Multi-channel Direct Digital Synthesizer
(eeProduct Center, 7/21/2005) -
Ultra-low Jitter Performance Marks Analog Devices' Entry into the Clock IC Market
(eeProductCenter, 12/8/04) -
Where Analog Really Meets Digital
(EE Time, 8/29/2005)
Reference Design (1)
Software and Tools (1)
-
ADIsimCLK Design and Evaluation Software
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
Solutions Bulletins (2)
Tutorials (2)
- MT-031: Grounding Data Converters and Solving the Mystery of (pdf, 144 kB)
- MT-101: Decoupling Techniques (pdf, 954 kB)
User Guides (2)
- UG-173: High Speed ADC USB FIFO Evaluation Kit (HSC-ADC-EVALB-DCZ) (pdf, 774 kB)
-
UG-207: Evaluation Board User Guide for AD9910
(pdf, 956 kB)
Evaluation Board for 1 GSPS DDS with 14-Bit DAC
Webcasts (2)
-
Fundamentals of Frequency Synthesis, Part 2: Direct Digital Synthesis (DDS)
This month we conclude our two-part series on frequency synthesis, with an introduction to Direct Digital Synthesis. We will give a basic review of how a direct digital synthesis system works, touching on the inner workings of the DDS engine at a relatively high level. We will also discuss the tradeoffs between PLL and DDS technology as a base choice for frequency synthesis needs. -
Performance Clocks: Demystifying Jitter
Join us as we delve into the realm of sub-picosecond jitter clocks. The relationship between jitter and phase noise will be explored in detail and methods for measuring sub-picosecond jitter and ultra low phase noise will be presented and discussed.
Analog Dialogue (8)
-
14-Bit Monolithic ADCs: First to Sample Faster than 1 MSPS
(Analog Dialogue, Vol. 31, No. 2, 1997) - ADC Input Noise: The Good, The Bad, and The Ugly. Is No Noise Good Noise?
-
Advanced Digital Post-Processing Techniques Enhance Performance in Time-Interleaved ADC Systems
by Mark Looney, Analog Devices, Inc. (Analog Dialogue, Vol. 37, June 2003) -
Analog-to-Digital Converter Clock Optimization: A Test Engineering Perspective
(Analog Dialogue, Vol. 42, February 2008) -
Ask The Application Engineer—33: All About Direct Digital Synthesis
(Analog Dialogue, Vol. 38, August 2004) -
Pushing the State of the Art with Multichannel A/D Converters
by Rob Reeder, Mark Looney and Jim Hand, Analog Devices, Inc. (Analog Dialogue, Vol. 39, May 2005) -
Transformer-Coupled Front-End for Wideband A/D Converters
by Rob Reeder, Analog Devices, Inc. (Analog Dialogue, Vol 39, April 2005) -
Ultrasound Analog Electronics Primer
(Analog Dialogue, Vol. 33, No. 5, May, 1999)