- JESD204B, Subclass 1 SYSREF Signal Generation
- Additive Output Jitter < 6fsRMS (Integration BW = 12kHz to 20MHz, f = 4.5GHz)
- Additive Output Jitter 65fsRMS (ADC SNR Method)
- EZSync™, ParallelSync™ Multichip Synchronization
- Eleven Independent, Low Noise Outputs with Programmable Coarse Digital and Fine Analog Delays
- Flexible Outputs Can Serve as Either a Device Clock or SYSREF Signal
- LTC6952Wizard Software Design Tool Support
- –40°C to 125°C Operating Junction Temperature Range
The LTC6953 is a high performance, ultralow jitter, JESD204B clock distribution IC. The LTC6953’s eleven outputs can be configured as up to five JESD204B subclass 1 device clock/SYSREF pairs plus one general purpose output or simply eleven general purpose clock outputs for non-JESD204B applications. Each output has its own individually programmable frequency divider and output driver. All outputs can also be synchronized and set to precise phase alignment using individual coarse half cycle digital delays and fine analog time delays.
For applications requiring more than eleven total outputs, multiple LTC6953s can be connected together with LTC6952s and LTC6955s using the EZSync or ParallelSync synchronization protocols.
- High Performance Data Converter Clocking
- Wireless Infrastructure
- Test and Measurement