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Volume 8, Issue 3 | YOUR SEMICONDUCTOR SOLUTIONS RESOURCE |
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C o n t e n t s iCMOS Switches and Multiplexers Enable Critical Systems Functions >> Digital Potentiometers Eliminate the Need for More Costly, Less Accurate Solutions >> Flexible Clocking Scheme for Multiple Wireless Standards >> Optimizing Signal Chain Performance with Voltage References >> Protect and Optimize Communication Networks with New Quad Channel Voltage Monitors and Sequencers >> Low Power Comparators with Integrated Reference and Programmable Hysteresis >> Protect Your Valuable Communication Networks with RS-232 and RS-485 IC >> Multivoltage Supervisor ICs Monitor Low Voltage Core Supplies for Peak Performance >> Online Supervisory IC Selection Tools from ADI >>
All prices in this bulletin are in USD in quantities greater than 1000 (unless otherwise noted), recommended lowest grade resale, FOB U.S.A.
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Flexible Clocking Scheme Accommodates Multiple Wireless Standards
To establish a clean and stable clock in wireless systems, designers typically employ a standard set of multiple discrete components including FPGA, filters, VCXO, PLL, and various clock distribution circuitry. However, this approach is undesirable because it often yields a complicated, high cost, low reliability clocking scheme, and consumes a large portion of the PCB area. In contrast, integrating critical timing functions onto higher function clock devices translates to using fewer components for lower overall cost, increased reliability, and a smaller footprint. As shown in the diagram below, multiple clock ICs may be combined to form a complete multifunction timing solution that addresses clock cleanup, generation, synchronization, and distribution, to meet the most stringent system requirements. In a remote radio unit (RRU), the incoming signal is cleaned up and then delivered to a clock generator to translate the frequency outputs to other system components. The ultraclean signal from the buffer goes through a SERDES to be sent back upstream. This clocking platform is ideal for digitizing a signal across multiple wireless standards, such as WiMAX, W-CDMA, CDMA2000, and CDMA.
Click here to view full size image The AD9549 clock generator/synchronizer cleans up a CDR clock using a digital PLL with a programmable loop bandwidth down to 0.1 Hz. The device provides reference monitoring and holdover functions. It delivers integrated jitter of <1 ps rms. An ultrafast 1:2 clock buffer, the ADCLK925, boasts fast output rise and fall times of 60 ps to maximize bandwidth and signal integrity. In addition, only 60 fs of random jitter is added on the outputs. The buffer distributes clean copies of the signal to both a SERDES and a flexible multioutput clock generator. The AD9516, AD9517, and AD9518, all with on-chip VCXO, offer excellent close-in phase noise performance when clocking multiple system components. The flexibility in selecting from multiple logic types and frequency combinations creates an ideal solution that can be used in various wireless systems. Five versions of each product are available with VCOs tuned from 1.45 GHz to 2.95 GHz. Clock Generation ICs
Clock Buffers
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