DI has expanded its industry-leading CDR technology by creating a new series of PON-optimized CDR and SERDES (serializer-deserializer) devices.

ADI has exploited its patented dual-loop CDR architecture to create the most cost-optimized GPON ONT SERDES available today. The CDR architecture that has resulted in ADI's industry-leading jitter generation, tolerance, and transfer performance is at the heart of the ADN2865, ADI's new loop-timed SERDES, that supports all PON data rates up to 2.5 Gbps.

The ADN2865 meets the required price, performance, and features for all GPON and BPON ONT SERDES needs. These features include the critical fixed latency requirement, minimal 8 mm × 8 mm LFCSP package, and minimal (<1 W) power dissipation. The SERDES has been designed to interface to the lowest cost FPGA devices to enable the highest performance with the maximum flexibility.

ADI has also created a line of pin-compatible fixed-rate CDR devices to complement ADI's 5 mm × 5 mm LFCSP continuous tuning family of CDR devices. To minimize cost for PON ONTs, these CDRs operate without reference clocks or external control. These ICs also maintain an accurate output clock in the absence of input data. To view our complete line of CDR and SERDES devices, visit www.analog.com/optical.

With ADI CDRs and SERDES ICs, you don't have to settle—get the industry's best J_TRAN and J_TOL.

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