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- SNR = 65 dB @ Fin up to 70 MHz @ 210 MSPS
- ENOB of 10.6 @ Fin up to 70 MHz @ 210 MSPS
- SFDR = 80 dBc @ Fin up to 70 MHz @ 210 MSPS
- Excellent Linearity:
- DNL = ±0.3 LSB (Typical)
- INL = ±0.5 LSB (Typical)
- Two Output Data Options:
- Demultiplexed 3.3 V CMOS Outputs Each @ 105 MSPS
- Interleaved or Parallel Data Output Option
- LVDS at 210 MSPS
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- 700 MHz Full Power Analog Bandwidth
- Power Dissipation = 1.3 W Typical @ 210 MSPS
- 1.5 V Input Voltage Range
- 3.3 V Supply Operation
- Output Data Format Option
- Data Sync Input and Data Clock Output Provided
- Clock Duty Cycle Stabilizer
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| Design Tools |
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High-Speed ADC FIFO Evaluation Kit
There are two high speed ADC evaluation kits available. The FIFO-based data acquisition board has a 32kB FIFO depth and acquires up to 133Msps on each channel. The FPGA-based data acquisition board has a 64kB FIFO depth and acquires up to 800Msps on each channel.
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AD9430 IBIS Models |
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